Hi Sachin,<br><br>Yes. Bernhard Scholz and I have just discussed a fix for this. I hope to commit it in the next few days. I will let you know as soon as it goes in to the mainline.<br><br>Regards,<br>Lang.<br><br><div class="gmail_quote">
On Tue, Dec 15, 2009 at 5:34 PM, <span dir="ltr"><<a href="mailto:Sachin.Punyani@microchip.com">Sachin.Punyani@microchip.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
Hi Lang,<br>
<br>
Thanks for your inputs on the problem. I was just curious to know if you got any opportunity to work on the solution for this.<br>
<br>
Regards<br>
Sachin<br>
<div><div></div><div class="h5"><br>
> -----Original Message-----<br>
> From: <a href="mailto:llvmdev-bounces@cs.uiuc.edu">llvmdev-bounces@cs.uiuc.edu</a> [mailto:<a href="mailto:llvmdev-bounces@cs.uiuc.edu">llvmdev-bounces@cs.uiuc.edu</a>] On<br>
> Behalf Of <a href="mailto:Sachin.Punyani@microchip.com">Sachin.Punyani@microchip.com</a><br>
> Sent: Tuesday, November 17, 2009 12:00 PM<br>
> Subject: Re: [LLVMdev] Crash in PBQP register allocator<br>
><br>
> Thanks Lang!<br>
><br>
> I think we can use linear scan as work around for short term.<br>
><br>
> Thanks for your help.<br>
><br>
> Regards<br>
> Sachin<br>
><br>
> > -----Original Message-----<br>
> > From: Lang Hames [mailto:<a href="mailto:lhames@gmail.com">lhames@gmail.com</a>]<br>
> > Sent: Sunday, November 15, 2009 10:08 AM<br>
> > To: Sachin Punyani - I00202<br>
> > Cc: <a href="mailto:llvmdev@cs.uiuc.edu">llvmdev@cs.uiuc.edu</a><br>
> > Subject: Re: [LLVMdev] Crash in PBQP register allocator<br>
> ><br>
> > Hi Sachin,<br>
> ><br>
> > Confirmed: This is being caused by a subtle issue in the heuristic<br>
> > PBQP solver. Specifically: R1/R2 reductions as currently implemented<br>
> > can, on rare occasions, lead to the heuristic solver failing to find a<br>
> > finite cost solution, even though one exists. The infinite cost<br>
> > solution will always be in violation of some rule of register<br>
> > allocation (failing to handle an interference, or spilling an infinite<br>
> > cost node for instance).<br>
> ><br>
> > There are several ways to fix the issue with the solver, but most<br>
> > would pesimmize allocation quality in the general case. I will look<br>
> > for a better solution when I return to the University of Sydney in a<br>
> > couple of weeks. In the mean time I have added an assert to the<br>
> > allocator to ensure that infinite cost solutions do not produce<br>
> > miscompilations. For programs which trigger the assert you'll just<br>
> > have to fall back on linear scan I'm afraid.<br>
> ><br>
> > (If you particularly want PBQP to work in the short term you could<br>
> > apply the following fix: Simply pre-color all infinite cost intervals<br>
> > and remove the register option from any live intervals with which they<br>
> > interfere).<br>
> ><br>
> > Cheers,<br>
> > Lang.<br>
> ><br>
> > On Thu, Nov 12, 2009 at 4:29 PM, Lang Hames <<a href="mailto:lhames@gmail.com">lhames@gmail.com</a>> wrote:<br>
> > > This looks like a bug in the PBQP solver. I'm currently investigating.<br>
> > ><br>
> > > Cheers,<br>
> > > Lang.<br>
> > ><br>
> > > On Thu, Nov 12, 2009 at 12:46 AM, <<a href="mailto:Sachin.Punyani@microchip.com">Sachin.Punyani@microchip.com</a>><br>
> wrote:<br>
> > >> Hi,<br>
> > >><br>
> > >><br>
> > >><br>
> > >> Please see the two ".ll' files attached.<br>
> > >><br>
> > >><br>
> > >><br>
> > >> Command line used<br>
> > >><br>
> > >> llc -march=pic16 -pre-RA-sched=list-burr -regalloc=pbqp new.obc<br>
> > >><br>
> > >><br>
> > >><br>
> > >> The above test case crashes only when I use the combination of list-<br>
> > burr<br>
> > >> scheduler and pbqp register allocator. If any of them (scheduler or<br>
> > register<br>
> > >> allocator) is replaced with some alternate then I don't see the<br>
> crash.<br>
> > >><br>
> > >><br>
> > >><br>
> > >> I could not figure out the reason. Please provide some pointers to<br>
> > reasons<br>
> > >> of the crash.<br>
> > >><br>
> > >><br>
> > >><br>
> > >> Regards<br>
> > >><br>
> > >> Sachin<br>
> > >><br>
> > >> _______________________________________________<br>
> > >> LLVM Developers mailing list<br>
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> > >> <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a><br>
> > >><br>
> > >><br>
> > ><br>
><br>
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</div></div></blockquote></div><br>