Index: ARMSubtarget.cpp
===================================================================
--- ARMSubtarget.cpp	(revision 90240)
+++ ARMSubtarget.cpp	(working copy)
@@ -38,6 +38,7 @@
   , UseNEONForSinglePrecisionFP(UseNEONFP)
   , IsThumb(isT)
   , ThumbMode(Thumb1)
+  , HasT2Divide(false)
   , PostRAScheduler(false)
   , IsR9Reserved(ReserveR9)
   , UseMovt(UseMOVT)
@@ -114,6 +115,9 @@
     if (UseNEONFP.getPosition() == 0)
       UseNEONForSinglePrecisionFP = true;
   }
+
+  if (CPUString == "cortex-m3")
+    HasT2Divide = true;
 }
 
 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
Index: ARMISelLowering.cpp
===================================================================
--- ARMISelLowering.cpp	(revision 90240)
+++ ARMISelLowering.cpp	(working copy)
@@ -349,8 +349,10 @@
     setOperationAction(ISD::BSWAP, MVT::i32, Expand);
 
   // These are expanded into libcalls.
-  setOperationAction(ISD::SDIV,  MVT::i32, Expand);
-  setOperationAction(ISD::UDIV,  MVT::i32, Expand);
+  if (!Subtarget->hasThumb2Divide()) {
+    setOperationAction(ISD::SDIV,  MVT::i32, Expand);
+    setOperationAction(ISD::UDIV,  MVT::i32, Expand);
+  }
   setOperationAction(ISD::SREM,  MVT::i32, Expand);
   setOperationAction(ISD::UREM,  MVT::i32, Expand);
   setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
Index: ARMSubtarget.h
===================================================================
--- ARMSubtarget.h	(revision 90240)
+++ ARMSubtarget.h	(working copy)
@@ -66,6 +66,9 @@
   /// imms (including global addresses).
   bool UseMovt;
 
+  /// HasT2Divide - True if thumb2 hardware divide instructions are available.
+  bool HasT2Divide;
+
   /// stackAlignment - The minimum alignment known to hold of the stack frame on
   /// entry to the function and which must be maintained by every function.
   unsigned stackAlignment;
@@ -126,6 +129,7 @@
   bool isThumb1Only() const { return IsThumb && (ThumbMode == Thumb1); }
   bool isThumb2() const { return IsThumb && (ThumbMode == Thumb2); }
   bool hasThumb2() const { return ThumbMode >= Thumb2; }
+  bool hasThumb2Divide() const { return HasT2Divide; }
 
   bool isR9Reserved() const { return IsR9Reserved; }
 
Index: ARMInstrThumb2.td
===================================================================
--- ARMInstrThumb2.td	(revision 90240)
+++ ARMInstrThumb2.td	(working copy)
@@ -954,7 +954,14 @@
 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
 
+def t2UDIV : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALUi,
+                 "udiv", "\t$dst, $a, $b",
+                 [(set GPR:$dst, (udiv GPR:$a, GPR:$b))]>;
 
+def t2SDIV : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALUi,
+                 "sdiv", "\t$dst, $a, $b",
+                 [(set GPR:$dst, (sdiv GPR:$a, GPR:$b))]>;
+
 //===----------------------------------------------------------------------===//
 //  Misc. Arithmetic Instructions.
 //
Index: ARM.td
===================================================================
--- ARM.td	(revision 90240)
+++ ARM.td	(working copy)
@@ -106,6 +106,7 @@
 def : Processor<"cortex-a8",        CortexA8Itineraries,
                 [ArchV7A, FeatureThumb2, FeatureNEON]>;
 def : ProcNoItin<"cortex-a9",       [ArchV7A, FeatureThumb2, FeatureNEON]>;
+def : ProcNoItin<"cortex-m3",       [ArchV7A, FeatureThumb2]>; 
 
 //===----------------------------------------------------------------------===//
 // Register File Description
