<html><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; ">The code sequence:<div><blockquote type="cite"><div><p><font size="2">store %tmp1, var<br>> tmp4 = add %tmp3 , %tmp1</font></p></div></blockquote><div><br></div><div>can happen even if you eliminate the specific dag combine in question. The real solution lies elsewhere. To me, this seems more like a register allocation problem.</div><div><br></div><div>Evan</div><div><br></div><div><div><div>On Mar 22, 2009, at 9:39 PM, <a href="mailto:Alireza.Moshtaghi@microchip.com">Alireza.Moshtaghi@microchip.com</a> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite">
<div>
<!-- Converted from text/plain format --><p><font size="2">I can't think of any workaround? this optimization eliminates so much information that if we want to retrieve back, it will take a lot of processing and may not necessarily be able to retrieve the lost information for all cases.<br>
Besides, why does the generic part of llvm have to force an optimization that is counter productive to some targets?<br>
If there are other phases that do the same optimization, I think we should also be able to disable them in those phases as well.<br>
<br>
A.<br>
<br>
<br>
-----Original Message-----<br>
From: <a href="mailto:llvmdev-bounces@cs.uiuc.edu">llvmdev-bounces@cs.uiuc.edu</a> on behalf of Dan Gohman<br>
Sent: Thu 3/19/2009 5:39 PM<br>
To: LLVM Developers Mailing List<br>
Subject: Re: [LLVMdev] Proposal to disable some of DAG combine optimizations<br>
<br>
Disabling this optimization in the DAG combiner isn't going to<br>
eliminate the problem; instcombine, GVN, and maybe even others also<br>
happen to perform this optimization. You may find it more effective<br>
to look for ways for codegen to recover in these kinds of situations.<br>
<br>
Dan<br>
<br>
On Mar 19, 2009, at 10:38 AM, <a href="mailto:Alireza.Moshtaghi@microchip.com">Alireza.Moshtaghi@microchip.com</a> wrote:<br>
<br>
> Some of the optimizations that the first DAG combine performs is <br>
> counter<br>
> productive for our 8-bit target. For example in:<br>
><br>
> // I dropped the types because they are irrelevant.<br>
> // Excuse me for changing the syntax...<br>
> store %tmp1, %var<br>
> %tmp2 = load %var<br>
> %tmp4 = add %tmp3, %tmp2<br>
><br>
> Since load is the only user of var and since var has just be stored <br>
> to,<br>
> it assumes that %tmp1 is alive and it goes ahead and removes the load<br>
> and does:<br>
><br>
> store %tmp1, var<br>
> tmp4 = add %tmp3 , %tmp1<br>
><br>
> This is great for architectures that have more than one registers<br>
> because it is likely that value of %tmp1 is already in a physical<br>
> register, hence saving an instruction. However for our 8-bit<br>
> architecture with only one register, this kind of assumptions will <br>
> just<br>
> result in extra overhead because "add" operates only on memory, so we<br>
> have to generate more instructions to store tmp1 to memory and then <br>
> use<br>
> that memory location for "add". But without the optimizations, we <br>
> could<br>
> just use var and everything would work out just fine.<br>
><br>
> So I propose to add a bit mask and a method to TargetLowering class so<br>
> targets can individually select some of the optimizations to be turned<br>
> off.<br>
><br>
> Thoughts?<br>
><br>
> Alireza Moshtaghi<br>
> Senior Software Engineer<br>
> Development Systems, Microchip Technology<br>
><br>
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</font>
</p>
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