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<TITLE>RE: [LLVMdev] Proposal to disable some of DAG combine optimizations</TITLE>
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<P><FONT SIZE=2>I can't think of any workaround? this optimization eliminates so much information that if we want to retrieve back, it will take a lot of processing and may not necessarily be able to retrieve the lost information for all cases.<BR>
Besides, why does the generic part of llvm have to force an optimization that is counter productive to some targets?<BR>
If there are other phases that do the same optimization, I think we should also be able to disable them in those phases as well.<BR>
<BR>
A.<BR>
<BR>
<BR>
-----Original Message-----<BR>
From: llvmdev-bounces@cs.uiuc.edu on behalf of Dan Gohman<BR>
Sent: Thu 3/19/2009 5:39 PM<BR>
To: LLVM Developers Mailing List<BR>
Subject: Re: [LLVMdev] Proposal to disable some of DAG combine optimizations<BR>
<BR>
Disabling this optimization in the DAG combiner isn't going to<BR>
eliminate the problem; instcombine, GVN, and maybe even others also<BR>
happen to perform this optimization. You may find it more effective<BR>
to look for ways for codegen to recover in these kinds of situations.<BR>
<BR>
Dan<BR>
<BR>
On Mar 19, 2009, at 10:38 AM, Alireza.Moshtaghi@microchip.com wrote:<BR>
<BR>
> Some of the optimizations that the first DAG combine performs is <BR>
> counter<BR>
> productive for our 8-bit target. For example in:<BR>
><BR>
> // I dropped the types because they are irrelevant.<BR>
> // Excuse me for changing the syntax...<BR>
> store %tmp1, %var<BR>
> %tmp2 = load %var<BR>
> %tmp4 = add %tmp3, %tmp2<BR>
><BR>
> Since load is the only user of var and since var has just be stored <BR>
> to,<BR>
> it assumes that %tmp1 is alive and it goes ahead and removes the load<BR>
> and does:<BR>
><BR>
> store %tmp1, var<BR>
> tmp4 = add %tmp3 , %tmp1<BR>
><BR>
> This is great for architectures that have more than one registers<BR>
> because it is likely that value of %tmp1 is already in a physical<BR>
> register, hence saving an instruction. However for our 8-bit<BR>
> architecture with only one register, this kind of assumptions will <BR>
> just<BR>
> result in extra overhead because "add" operates only on memory, so we<BR>
> have to generate more instructions to store tmp1 to memory and then <BR>
> use<BR>
> that memory location for "add". But without the optimizations, we <BR>
> could<BR>
> just use var and everything would work out just fine.<BR>
><BR>
> So I propose to add a bit mask and a method to TargetLowering class so<BR>
> targets can individually select some of the optimizations to be turned<BR>
> off.<BR>
><BR>
> Thoughts?<BR>
><BR>
> Alireza Moshtaghi<BR>
> Senior Software Engineer<BR>
> Development Systems, Microchip Technology<BR>
><BR>
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