<html><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; "><br><div><div>On Feb 19, 2009, at 8:26 PM, 任坤 wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><table cellspacing="0" cellpadding="0" border="0" style="position: static; z-index: auto; "><tbody><tr><td valign="top" style="font: inherit;"><div id="yiv110945996">hi, Dear Evan Cheng:<br><br>My cpu is i32 embeded CPU. I define pseudo register pair registers.<br><br>In mytargetRegisterInfo.td:<br>def T0: RegisterWithSubRegs<"t0",[R0,R1]>;<br>...<br>def GPR64 : RegisterClass<"mytarget", [i64], 64, [T0, T1.....]<br><br>In mytargetISelLowering.cpp:<br>I define i1, i8 , i16 and i32 are legal. <br><br>1. I still have problem. I save my function return double value in R0 and R1. <br> It is expanded into two i32. But my GPR64 is defined to save i64. llvm finds<br> I have i64 GPR register. It will automatically decide not to expand i64 to two i32.<br><br>2. I guess I need a special pseudo instruction to move between GPR32 and GPR64.<br>How to move R0, R1 to T1( R2, R3 pair). and don't convert two i32 to i64?<br>Could I use MyTargetInstrInfo::copyRegToReg() to handle this logic issue?</div></td></tr></tbody></table></blockquote><div><br></div>No. copyRegToReg only supports copying registers of the same (or compatible register classes).</div><div><br><blockquote type="cite"><table cellspacing="0" cellpadding="0" border="0" style="position: static; z-index: auto; "><tbody><tr><td valign="top" style="font: inherit;"><div id="yiv110945996"><br><br>3. Maybe I can study INSERT_SUBREG/EXTRACT_SUBREG at X86 porting file.</div></td></tr></tbody></table></blockquote><div><br></div>Yes.</div><div><br><blockquote type="cite"><table cellspacing="0" cellpadding="0" border="0" style="position: static; z-index: auto; "><tbody><tr><td valign="top" style="font: inherit;"><div id="yiv110945996"><br><br>I will do some research more deeply. I think the best way is that TableGen has register pair TypeProfile feature. :( </div></td></tr></tbody></table></blockquote><div><br></div>It's not a tablegen issue. It's easy to add the constraint to tablegen but the register allocator has to be able to allocate register pairs. That is definitely not a trivial task.</div><div><br></div><div>Evan</div><div><br><blockquote type="cite"><table cellspacing="0" cellpadding="0" border="0" style="position: static; z-index: auto; "><tbody><tr><td valign="top" style="font: inherit;"><div id="yiv110945996"><br><br><br><br><br>But I find i64 data will not be ex<br>--- <b>09年2月20日，周五, Evan Cheng <i><<a href="mailto:echeng@apple.com">echeng@apple.com</a>></i></b> 写道：<br><blockquote style="border-left-color: #1010ff; border-left-width: 2px; border-left-style: solid; margin-left: 5px; padding-left: 5px">发件人: Evan Cheng <<a href="mailto:echeng@apple.com">echeng@apple.com</a>><br>主题: Re: [LLVMdev] help: about how to use tblgen to constraint operand.<br>收件人: <a href="mailto:hbrenkun@yahoo.cn">hbrenkun@yahoo.cn</a>, "LLVM Developers Mailing List" <<a href="mailto:llvmdev@cs.uiuc.edu">llvmdev@cs.uiuc.edu</a>><br>日期: 2009,220,周五,1:11上午<br><br><div id="yiv2016100483">Currently there is no constraint that tells the register allocator to allocate a consecutive register pair. What I would suggest you do is to declare pseudo register pair registers (and corresponding register class, say PAIR_GPR). In this case, your myFMDRR would take one input of PAIR_GPR class. The asm printer should be taught to print a PAIR_GPR register as two GPR registers (you should also teach the JIT of the same thing).<div><br></div><div>A PAIR_GPR register should be a super register of two GPR registers. e.g. r0r1_pair is a super register of r0 and r1. In order to *construct* a PAIR_GPR register, you have to use two INSERT_SUBREG. To extract out a GPR from a PAIR_GPR, you need to issue EXTRACT_SUBREG. In most cases, these will be nop's. In other cases, they are copies.</div><div><br></div><div>Evan</div><div><br><div><div>On Feb 19, 2009, at 2:00 AM, 任坤 wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><table cellspacing="0" cellpadding="0" border="0"><tbody><tr><td valign="top" style="font-style: inherit; font-variant: inherit; font-weight: inherit; font-size: inherit; line-height: inherit">I define a pattern to move two 32bits gpr to 64bits fpr. like arm instructure fmdrr.<br>But I need to use an even/odd register pair to save its 2 operands.<br>I define in mytarget.td:<br><br>myfmdrr:<br> SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,<br> SDTCisSameAs<1, 2>]>;<br>def my_fmdrr : ...........<br>def myFMDRR : ....<br> (outs FPR: $result), ins(GPR: $op1, GPR:$op2 )<br> [(setFPR: $result, (my_fmdrr GPR: $op1, GPR:$op2) )]<br><br>I create myfmdrr instructure in mytargetISelLowering.cpp. and its operands are in R0 and R1.<br>But after optimization, the operands are save R2 and R1. I know optimization pass does not <br>know myfmdrr operands constraint. But How I tell optimzition pass by tblgen??<br><br>Could I can control operand constraint in mytargetiSelLowering.cpp? How do I control?? <br><br></td></tr></tbody></table><br><hr size="1"><a rel="nofollow" target="_blank" href="http://cn.rd.yahoo.com/mail_cn/tagline/card/*http://card.mail.cn.yahoo.com/"> 好玩贺卡等你发，邮箱贺卡全新上线！</a>_______________________________________________<br>LLVM Developers mailing list<br><a href="mailto:LLVMdev@cs.uiuc.edu">LLVMdev@cs.uiuc.edu</a> <a rel="nofollow" target="_blank" href="http://llvm.cs.uiuc.edu">http://llvm.cs.uiuc.edu</a><br><a rel="nofollow" target="_blank" href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a><br></blockquote></div><br></div></div></blockquote></div></td></tr></tbody></table><br> <hr size="1"><a href="http://cn.rd.yahoo.com/mail_cn/tagline/card/*http://card.mail.cn.yahoo.com/"> 好玩贺卡等你发，邮箱贺卡全新上线！</a>_______________________________________________<br>LLVM Developers mailing list<br><a href="mailto:LLVMdev@cs.uiuc.edu">LLVMdev@cs.uiuc.edu</a> <a href="http://llvm.cs.uiuc.edu">http://llvm.cs.uiuc.edu</a><br><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a><br></blockquote></div><br></body></html>