<html><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; ">Why not model each channel as a separate physical register?<div><br></div><div>Evan</div><div><br><div><div>On Nov 17, 2008, at 6:36 AM, Wei wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite">I have a very strange and complicate H/W platform.<br>It has many registers in one format.<br>The register format is:<br><br>------------------------------<div>----------------------------------------------------------------------------------------<br> | 24-bit | 24-bit | 24-bit | 24-bit |<br>----------------------------------------------------------------------------------------------------------------------<br> a b c d<br><br>There are 4 channels in a register, and each channel contains 24-bit, hence, there are total 96-bit in 'one' register.<br> You can store a 24-bit integer or a s7.16 floating-point data into each channel.<br>You can name each channel 'a', 'b', 'c', 'd'.<br><br>Here is an example of the operation in this H/W platform:<br> <br> ADD R3.ab, R1.abab, R2.bbaa<br><br>it means<br><br> Add 'abab' channel of R1 and 'bbaa' channel of R2, and put the result into the 'ab' channel of R3.<br><br>It's complicate.<br> Imagine a non-existed temp register named 'Rt1', the content of its 'a','b','c','d' channel are got from 'a','b','a','b' channel of R1,<br>and imagine another non-existed temp register named 'Rt2', the content of its 'a','b','c','d' channel are got from 'b','b','a','a' channel of R2.<br> and then add Rt1 & Rt2, put the result to R3<br>this means<br>the 'a' channel of R3 will be equal to the 'a' channel of Rt1 plus the 'a' channel of Rt2, (i.e. 'a' from R1 + 'b' from R2, because R1.'a'bab and R2.'b'baa)<br> the 'b' channel of R3 will be equal to the 'b' channel of Rt1 plus the 'b' channel of Rt2, (i.e. 'b' from R1 + 'b' from R2, because R1.a'b'ab and R2.b'b'aa)<br>the 'c' channel of R3 will be untouched, the value of the 'c' channel of Rt1 plus the 'c' channel of Rt2 (i.e. 'a' from R1 + 'a' from R2, because R1.ab'a'b and R2.bb'a'a) will be lost.<br> the 'd' channel of R3 will be untouched, too. The value of the 'd' channel of Rt1 plus the 'd' channel of Rt2 (i.e. 'b' from R1 + 'a' from R2, because R1.aba'b' and R2.bba'a') will be lost, too.<br> <br>I don't know whether I can set the 'type' of such register using a llvm::MVT::SimpleValueType?<br>According the LLVM doc & LLVM source codes, I think llvm::MVT::v8i8, v2f32, etc is used to represent register for SIMD instructions.<br> I don't think the operations in my platform are SIMD instructions.<br>However, I can not find any llvm::MVT::SimpleValueType which can represents a 96-bit register.<br><br>Thus, my question is:<br><br>1) Does current LLVM backend supports this H/W?<br> 2) If yes, how can I write the type of the register class in my .td file?<br><br>(Which value should I fill in the following 'XXX' ?)<br>def TempRegs : RegisterClass<"MFLEXG", [XXX], 32, [R0, R1, R2, R3, R4, R5, R6, R7, R8, R9,<br> R10, R11, R12, R13, R14, R15, R16, R17, R18, R19,<br> R20, R21, R22, R23, R24, R25, R26, R27, R28, R29,<br> R30, R31]> {<br> }<br><br>3) If not, does this means I have to write the whole LLVM backend based on the basic llvm::TargetMachine & llvm::TargetData, just like what CBackend does?<br><br><br>--------------------------------------------------------<br></div>Wei Hu<br><a href="http://www.csie.ntu.edu.tw/%7Er88052/" target="_blank">http://www.csie.ntu.edu.tw/~r88052/</a><br><a href="http://wei-hu-tw.blogspot.com/" target="_blank">http://wei-hu-tw.blogspot.com/</a><br> <br> _______________________________________________<br>LLVM Developers mailing list<br><a href="mailto:LLVMdev@cs.uiuc.edu">LLVMdev@cs.uiuc.edu</a> <a href="http://llvm.cs.uiuc.edu">http://llvm.cs.uiuc.edu</a><br><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a><br></blockquote></div><br></div></body></html>