<html><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; "><br><div><div>On Nov 10, 2008, at 8:05 PM, Dan Gohman wrote:</div><blockquote type="cite"><div><font class="Apple-style-span" color="#000000"><br></font>What version of LLVM are you using? I recently made some tablegen<br>changes to allow nodes to have multiple predicates. See r57565 for<br>an example of a change made possible by being able to have multiple<br>predicates on a node, and it sounds similar to what you describe.</div></blockquote><div><br></div><div>I retried this fairly recently, but it's worth trying again.</div><div><br></div><blockquote type="cite"><div><blockquote type="cite"><br></blockquote><blockquote type="cite">(2) The HW I'm targeting does not have byte/short load/store; the<br></blockquote><blockquote type="cite">finest granularity is aligned 32 bit load/store (like the original<br></blockquote><blockquote type="cite">Alpha architecture). In addition, I want to optimize certain vector<br></blockquote><blockquote type="cite">operations (128 bit load/store) and some are getting converted from 32<br></blockquote><blockquote type="cite">bit to multiple 8 bit operations (e.g. store a 4 element vector of<br></blockquote><blockquote type="cite">chars becomes 4 one byte stores), but I don't want to provide full<br></blockquote><blockquote type="cite">vector register support (at this time).<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">Any hints on a good approach to dealing with the 32 bit aligned load/<br></blockquote><blockquote type="cite">store limitations and mixing and matching "native" load/store support<br></blockquote><blockquote type="cite">of vector types with LLVM generated expansions of vector operations?<br></blockquote><br>For the 32-bit load/store question, I think you should mark<br>loads and stores of i8 and i16 as Custom, which will allow<br>you to write target-specific code to handle them. For the<br>vector question, it sounds like a target-specific DAGCombine<br>may be a possible solution.</div></blockquote><div><br></div><div>For custom load/stores, is there an existing sample I could use as a template?</div><div><br></div><div>I have been looking at the SPU code: It seems it generates a custom ISD node, LDRESULT, which it then custom selects code for.</div><div><br></div><div>I have not been able to successfully create a custom load node which I can then use a pattern match select on.</div><div><br></div><div>During selection, it tries to get info on the mem operand, and I that information doesn't seem to exist (I create my original LDRESULT equivalent with a simple getNode, which I suspect doesn't set up all the mem operand type information?).</div><div><br></div><div>In particular, I keep asserting in the getSizeInBits. The match calls getMemoryVT().getSizeInBits, which then goes to getVectorElementType.getSizeInBits(). The getMemoryVT() result seems to be where the garbage is introduced (the V value is way out of range), which is why I'm guessing it's not being set up.</div><div><br></div><div>Once I get through this, I'll look into the combining question...</div><div><br></div><div>Thanks,</div><div><br></div><div>Dan</div><div><br></div><blockquote type="cite"><div><br>Dan<br><br>_______________________________________________<br>LLVM Developers mailing list<br><a href="mailto:LLVMdev@cs.uiuc.edu">LLVMdev@cs.uiuc.edu</a> <a href="http://llvm.cs.uiuc.edu">http://llvm.cs.uiuc.edu</a><br><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a><br></div></blockquote></div><br></body></html>