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<p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
10.0pt;font-family:Arial;color:navy'>Sanjay, I am working on backend with similar
constraints using Method #1. You can use createVirtualRegister for all your
register allocation needs. The only issue is that it currently resets the
virtual register count at the beginning of each function call. Look at the
thread, “Virtual Register allocation across functions” to see
possible solutions for this issue.<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
10.0pt;font-family:Arial;color:navy'><o:p> </o:p></span></font></p>
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<p class=MsoNormal><b><font size=2 face=Tahoma><span style='font-size:10.0pt;
font-family:Tahoma;font-weight:bold'>From:</span></font></b><font size=2
face=Tahoma><span style='font-size:10.0pt;font-family:Tahoma'>
llvmdev-bounces@cs.uiuc.edu [mailto:llvmdev-bounces@cs.uiuc.edu] <b><span
style='font-weight:bold'>On Behalf Of </span></b>Sanjay Soman<br>
<b><span style='font-weight:bold'>Sent:</span></b> Tuesday, October 28, 2008
11:41 AM<br>
<b><span style='font-weight:bold'>To:</span></b> llvmdev@cs.uiuc.edu<br>
<b><span style='font-weight:bold'>Subject:</span></b> [LLVMdev] Targeting a
platform with virtual instruction set andunlimited virtual registers</span></font><o:p></o:p></p>
<p class=MsoNormal><font size=3 face="Times New Roman"><span style='font-size:
12.0pt'><o:p> </o:p></span></font></p>
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<p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><font
size=2 face=Arial><span style='font-size:10.0pt;font-family:Arial'>I am
working on a LLVM backend for a new platform. The target has a virtual
instruction set and unlimited virtual registers. After going through LLVM
documentation and source code, it looks like there are two possible ways to
implement it with LLVM:<o:p></o:p></span></font></p>
<p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><font
size=2 face=Arial><span style='font-size:10.0pt;font-family:Arial'>1) Method
#1: follow common code generator path (TableGen, LLVMTargetMachine, etc),
similarly as the Sparc and x86 targets. Since the target has unlimited number
of virtual registers, register allocation is no use here. I can skip the
register allocation by overloading the register allocator with one does no
allocation. Is there any assumption in this infrastructure that would prevent
from doing so?<o:p></o:p></span></font></p>
<p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><font
size=2 face=Arial><span style='font-size:10.0pt;font-family:Arial'>2) Method
#2: follow the custom code generator path, similar as the CBackend and MSIL
targets.<o:p></o:p></span></font></p>
<p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><font
size=2 face=Arial><span style='font-size:10.0pt;font-family:Arial'><o:p> </o:p></span></font></p>
<p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><font
size=2 face=Arial><span style='font-size:10.0pt;font-family:Arial'>Iąd like
to evaluate which method is more appropriate for this particular target.
Method#1 provides some optimizations at machine instruction level (in this
case, the virtual instruction set). Is the custom path capable of doing the
same?</span></font><o:p></o:p></p>
<p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><font
size=3 face="Times New Roman"><span style='font-size:12.0pt'> <o:p></o:p></span></font></p>
<p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><font
size=2 face=Arial><span style='font-size:10.0pt;font-family:Arial'>Thanks,</span></font><o:p></o:p></p>
<p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><font
size=2 face=Arial><span style='font-size:10.0pt;font-family:Arial'>-Sanjay</span></font><o:p></o:p></p>
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