<html><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; "><br><div><div>On Oct 18, 2008, at 7:01 AM, sanjiv gupta wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div>On Thu, 2008-10-16 at 08:55 -0700, Evan Cheng wrote:<br><blockquote type="cite">On Oct 15, 2008, at 11:21 AM, sanjiv gupta wrote:<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><br></blockquote></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite">Ok. The AX / AH super-reg and sub-reg relationship is not defined. In<br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite">general x86 is not making good use of the high 8-bit sub-registers. <br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite">We<br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite">are leaving some performance on the table. We'll probably fix it one<br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite">day. However, this doesn't apply to your target, right? There is<br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite">nothing preventing you from specifying the sub-registers and making<br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite">use of insert_subreg, no?<br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite">Evan<br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">it is, though we have a workaround.<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">We have 16-bit registers class and want to set both the lo and high<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">parts using INSERT_SUBREG.<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">The workaround is to declare the same SubRegClass twice while <br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">declaring<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">the SuperRegisterClass. i.e.<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> {<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"> let SubRegClassList = [FSR8, FSR8]; // HERE.<br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite">}<br></blockquote></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">This is a bug, probably in tablegen. Unfortunately I don't have the <br></blockquote><blockquote type="cite">time to fix it. But please file a bug about this. Hopefully someone <br></blockquote><blockquote type="cite">will fix it soon.<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">Thanks,<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">Evan<br></blockquote><blockquote type="cite"><br></blockquote><br>PR2916 filed.<br>Though I did not quite understand why this could be a tablegen bug?</div></blockquote><div><br></div>Based on your comments. :-) It should be possible to specify two FSR0 sub-registers (FSR0L, FSR0H of the same register class FSR8) with the workaround you described:</div><div><br></div><div><span class="Apple-style-span" style="font-family: -webkit-monospace; font-size: 11px; ">def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> {<br> let SubRegClassList = [FSR8, FSR8]; // HERE.<br>}</span></div><div><font class="Apple-style-span" face="-webkit-monospace" size="3"><span class="Apple-style-span" style="font-size: 11px;"><br></span></font></div><div><font class="Apple-style-span" face="-webkit-monospace" size="3"><span class="Apple-style-span" style="font-size: 11px;">Evan</span></font></div><div><br><blockquote type="cite"><div><br><br>- Sanjiv<br><br><br>_______________________________________________<br>LLVM Developers mailing list<br>LLVMdev@cs.uiuc.edu <a href="http://llvm.cs.uiuc.edu">http://llvm.cs.uiuc.edu</a><br><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a><br></div></blockquote></div><br></body></html>