<html><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; ">Well, consider the multiply doesn't touch memory and is independent on any outputs or side effects of llvm.soru.sre intrinsics, codegen is free to reorder the two. It may require llvm extension to model an instruction that has this level of side effects. One possible short term workaround is to move the intrinsic instruction into its own basic block. But they may not work if codegen prepare sink any instruction past it or when we switch to beyond basic block instruction selection.<div><br></div><div>Evan<br><div><br><div><div>On Sep 15, 2008, at 12:16 AM, Julio wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div dir="ltr">Nothing... I'll show you all the info related to:<br><br>The intrinsic: def int_soru_sre : Intrinsic<[llvm_void_ty, llvm_i32_ty], [IntrWriteMem]>;<br><br>The lower instruction (in MIPS):<br>class SORUI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,<br> InstrItinClass itin>: FI<op, outs, ins, asmstr, pattern, itin><br>{<br> let isBarrier = 1; // or call, hassideefects, ..., nothing work<br>}<br><br>def SORU_SRE: SORUI<0b110011, (outs), (ins uimm16:$imm), "sre $imm",<br> [(int_soru_sre imm:$imm)], IISoru>;<br><br>(With IISoru I made all the possible changes: a lot of cycles or none with all the functional units or none)<br><br>And an example:<br> tail call void @llvm.soru.sre( i32 5 )<br> mul i32 %b, %a ; <i32>:0 [#uses=1]<br><br>is coded as:<br><br> mult $2, $5, $4<br> sre 5<br><br>Best regards.<br>Julio<br><br><div class="gmail_quote">2008/9/14 Anton Korobeynikov <span dir="ltr"><<a href="mailto:asl@math.spbu.ru">asl@math.spbu.ru</a>></span><br> <blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">Hello, Julio<br> <div class="Ih2E3d"><br> > These later things are ignored, I don't know if when the intrinsic is<br> > lowered, then it doesn't matter (or perhaps the reorder is made<br> > before).<br> </div>What is the description of the instruction you're lowering intrinsic<br> into? Have you looked for the instruction flags defined in Target.td<br> file? You instruction should definitely have "isBarrier" flag set.<br> <br> --<br> With best regards, Anton Korobeynikov.<br> <br> Faculty of Mathematics & Mechanics, Saint Petersburg State University.<br> <br> _______________________________________________<br> LLVM Developers mailing list<br> <a href="mailto:LLVMdev@cs.uiuc.edu">LLVMdev@cs.uiuc.edu</a> <a href="http://llvm.cs.uiuc.edu" target="_blank">http://llvm.cs.uiuc.edu</a><br> <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a><br> </blockquote></div><br></div> _______________________________________________<br>LLVM Developers mailing list<br><a href="mailto:LLVMdev@cs.uiuc.edu">LLVMdev@cs.uiuc.edu</a> <a href="http://llvm.cs.uiuc.edu">http://llvm.cs.uiuc.edu</a><br><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a><br></blockquote></div><br></div></div></body></html>