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<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>So, I have this small test program that I figured would
cause no problems but want to test all the various data types and operations
with my modified sparc backend. I’ve been working on LLVM for about 3
days now, so this might be a problem with not knowing enough yet, so thanks for
bearing with me.<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>The code that I based my example off of is compiled to
LLVM-IR from:<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>void test_unary_op_anegate(float x, float* result)<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>{<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'> *result = (-x);<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>}<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>Generating the following LLVM IR:<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>define void @test_unary_op_anegate(float %x, float
addrspace(11)* %result) nounwind {<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>entry:<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'> %neg = sub float
-0.000000e+000,
%x ;
<float> [#uses=1]<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'> store float %neg,
float addrspace(11)* %result<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'> ret void<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>}<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>However, when I attempt to run it through my backend which
can handle binary math ops correctly I keep asserting on the following item.<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>Cannot yet select: 017B8010: i32 = fneg 017B7E78<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>What I cannot figure out is why it is attempting to pattern
match on an i32 when there are no i32’s in my test program.<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>I’ve tried a custom lowering function that lowers it
to dst = sub 0, src0 and forcing it to f32, but it complains that result and
the op value types are incorrect.<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>My table descriptor rule is:<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>def FNEG :
OneInOneOut<OP_F_NEG, (outs GPR:$dst), (ins GPR:$src0),<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>
!strconcat(OP_F_NEG.Text, " $dst, $src0"),<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>
[(set GPR:$dst, (fneg GPR:$src0))]>;<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>With GPR defined as either an i32 or an f32.<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>On another not, is there any known examples of using Tablegen
with a typeless register class? Or with instruction formats where the modifiers
are on the registers and the instructions(i.e. mul_x2 GPR0, GPR1_neg, GPR2_abs,
which is equivalent to GPR0 = (-GPR1 * abs(GPR2)*2)?<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>Thanks,<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>Micah Villmow<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>Systems Engineer<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>Advanced Technology & Performance<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>Advanced Micro Devices Inc.<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'><ns0:Street w:insAuthor="Micah Villmow"
w:insDate="2008-09-10T14:19:00Z" w:endInsAuthor="Micah Villmow"
w:endInsDate="2008-09-10T14:19:00Z"><ns0:address w:insAuthor="Micah Villmow"
w:insDate="2008-09-10T14:19:00Z" w:endInsAuthor="Micah Villmow"
w:endInsDate="2008-09-10T14:19:00Z"><st1:Street w:st="on"><st1:address w:st="on">4555
Great America Pkwy</st1:address></st1:Street></ns0:address></ns0:Street>,<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'><ns0:place w:insAuthor="Micah Villmow"
w:insDate="2008-09-10T14:19:00Z" w:endInsAuthor="Micah Villmow"
w:endInsDate="2008-09-10T14:19:00Z"><ns0:City w:insAuthor="Micah Villmow"
w:insDate="2008-09-10T14:19:00Z" w:endInsAuthor="Micah Villmow"
w:endInsDate="2008-09-10T14:19:00Z"><st1:City w:st="on"><st1:place w:st="on">Santa
Clara</st1:place></st1:City></ns0:City></ns0:place>, CA. 95054<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>P: 408-572-6219<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>F: 408-572-6596</span></font><font size=2 face=Arial><span
style='font-size:10.0pt;font-family:Arial'><o:p></o:p></span></font></p>
<p class=MsoNormal><font size=3 face="Times New Roman"><span style='font-size:
12.0pt'><o:p> </o:p></span></font></p>
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