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<p class=MsoNormal>Hi all,<o:p></o:p></p>
<p class=MsoNormal><o:p> </o:p></p>
<p class=MsoNormal>How do I generate the movq2dq SSE2 instruction using the
IRBuilder? There is no zext from 64-bit to 128-bit (corresponding to MMX to XMM
register transfer) as far as I can tell. So I’ve tried inserting an i64
into a v2i64, which generates valid code but rather a number of stores and
loads on the stack instead of a single movq2dq.<o:p></o:p></p>
<p class=MsoNormal><o:p> </o:p></p>
<p class=MsoNormal>Looking though the code, I found a pattern for the
instruction in X86GenDAGISEL.inc, but it describes a i64 to v2i64 bitcast
(which isn’t allowed by IRBuilder). Also, it is described as <span
style='font-size:10.0pt;font-family:"Courier New"'>MMX_MOVQ2DQrr</span> and
only checks for MMX support, while it’s really an SSE2 instruction.<o:p></o:p></p>
<p class=MsoNormal><o:p> </o:p></p>
<p class=MsoNormal>Actually zext from 32 to 64 and 32 to 128 bit would also be
useful, using movd and movq instructions. I couldn’t find ways to
generate these instructions. I believe they should also be supported as
intrinsics, so if anyone could check whether or not that works, and if so, how
I could do it using the IRBuilder, that would be very much appreciated.<o:p></o:p></p>
<p class=MsoNormal><o:p> </o:p></p>
<p class=MsoNormal>Cheers,<o:p></o:p></p>
<p class=MsoNormal><o:p> </o:p></p>
<p class=MsoNormal>Nicolas Capens<o:p></o:p></p>
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