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<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>Hi,</span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>I have started to write an llvm backend for one of our
microcontrollers (PICxx). I started studying the framework of PowerPc backend
of llvm and decided to start by following that framework. Now I have most of
the classes and Tblgen files written for a very basic hypothetical
microcontroller with very few instructions.</span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>The project builds and the llc recognizes the new processor,
however, when it reaches the point where it wants to lower llvm IR to PICxx DAG,
it asserts in LegalizeDAG.cpp in ExpandOp() function after it hits the default
case of switch(Node->getOpcode())</span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>Can someone please help me understand how am I ending up in
the default case?</span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'> </span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>Thanks,</span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>A.</span></font></p>
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