Index: configure.in
===================================================================
--- configure.in	(revision 39923)
+++ configure.in	(working copy)
@@ -774,6 +774,9 @@
     ;;
   sparc-*-solaris* | sparc64-*-solaris* | sparcv9-*-solaris*)
     ;;
+  spu-*-*)
+    skipdirs="target-libiberty"
+    ;;
   v810-*-*)
     noconfigdirs="$noconfigdirs bfd binutils gas gcc gdb ld target-libstdc++-v3 opcodes target-libgloss ${libgcj}"
     ;;
Index: configure
===================================================================
--- configure	(revision 39923)
+++ configure	(working copy)
@@ -1618,6 +1618,9 @@
     ;;
   sparc-*-solaris* | sparc64-*-solaris* | sparcv9-*-solaris*)
     ;;
+  spu-*-*)
+    skipdirs="target-libiberty"
+    ;;
   v810-*-*)
     noconfigdirs="$noconfigdirs bfd binutils gas gcc gdb ld target-libstdc++-v3 opcodes target-libgloss ${libgcj}"
     ;;
Index: gcc/doc/extend.texi
===================================================================
--- gcc/doc/extend.texi	(revision 39923)
+++ gcc/doc/extend.texi	(working copy)
@@ -2123,8 +2123,8 @@
 
 @item naked
 @cindex function without a prologue/epilogue code
-Use this attribute on the ARM, AVR, C4x and IP2K ports to indicate that the
-specified function does not need prologue/epilogue sequences generated by
+Use this attribute on the ARM, AVR, C4x, IP2K and SPU ports to indicate that
+the specified function does not need prologue/epilogue sequences generated by
 the compiler.  It is up to the programmer to provide these sequences.
 
 @item near
@@ -3615,6 +3615,12 @@
 For documentation of @code{altivec} attribute please see the
 documentation in the @xref{PowerPC Type Attributes}, section.
 
+@subsection SPU Variable Attributes
+
+The SPU supports the @code{spu_vector} attribute for variables.  For
+documentation of this attribute please see the documentation in the
+@xref{SPU Type Attributes}, section.
+
 @subsection Xstormy16 Variable Attributes
 
 One attribute is currently defined for xstormy16 configurations:
@@ -3994,6 +4000,15 @@
 These attributes mainly are intended to support the @code{__vector},
 @code{__pixel}, and @code{__bool} AltiVec keywords.
 
+@anchor{SPU Type Attributes}
+@subsection SPU Type Attributes
+
+The SPU supports the @code{spu_vector} attribute for types.  This attribute
+allows one to declare vector data types supported by the Sony/Toshiba/IBM SPU
+Language Extensions Specification.  It is intended to support the
+@code{__vector} keyword.
+
+
 @node Inline
 @section An Inline Function is As Fast As a Macro
 @cindex inline functions
@@ -6473,6 +6488,7 @@
 * MIPS Paired-Single Support::
 * PowerPC AltiVec Built-in Functions::
 * SPARC VIS Built-in Functions::
+* SPU Built-in Functions::
 @end menu
 
 @node Alpha Built-in Functions
@@ -10106,6 +10122,62 @@
 int64_t __builtin_vis_pdist (v8qi, v8qi, int64_t);
 @end smallexample
 
+@node SPU Built-in Functions
+@subsection SPU Built-in Functions
+
+GCC provides extensions for the SPU processor as described in the
+Sony/Toshiba/IBM SPU Language Extensions Specification, which can be
+found at @uref{http://cell.scei.co.jp/} or
+@uref{http://www.ibm.com/developerworks/power/cell/}.  GCC's
+implementation differs in several ways.
+
+@itemize @bullet
+
+@item
+The optional extension of specifying vector constants in parentheses is
+not supported.
+
+@item
+A vector initializer requires no cast if the vector constant is of the
+same type as the variable it is initializing.
+
+@item
+If @code{signed} or @code{unsigned} is omitted, the signedness of the
+vector type is the default signedness of the base type.  The default
+varies depending on the operating system, so a portable program should
+always specify the signedness.
+
+@item
+By default, the keyword @code{__vector} is added. The macro
+@code{vector} is defined in @code{<spu_intrinsics.h>} and can be
+undefined.
+
+@item
+GCC allows using a @code{typedef} name as the type specifier for a
+vector type.
+
+@item
+For C, overloaded functions are implemented with macros so the following
+does not work:
+
+@smallexample
+  spu_add ((vector signed int)@{1, 2, 3, 4@}, foo);
+@end smallexample
+
+Since @code{spu_add} is a macro, the vector constant in the example
+is treated as four separate arguments.  Wrap the entire argument in
+parentheses for this to work.
+
+@item
+The extended version of @code{__builtin_expect} is not supported.
+
+@end itemize
+
+@emph{Note:} Only the interface descibed in the aforementioned
+specification is supported. Internally, GCC uses built-in functions to
+implement the required functionality, but these are not supported and
+are subject to change without notice.
+
 @node Target Format Checks
 @section Format Checks Specific to Particular Target Machines
 
Index: gcc/doc/invoke.texi
===================================================================
--- gcc/doc/invoke.texi	(revision 39923)
+++ gcc/doc/invoke.texi	(working copy)
@@ -825,6 +825,13 @@
 -mv8plus  -mno-v8plus  -mvis  -mno-vis
 -threads -pthreads -pthread}
 
+@emph{SPU Options}
+@gccoptlist{-mwarn-reloc -merror-reloc @gol
+-msafe-dma -munsafe-dma @gol
+-mbranch-hints @gol
+-msmall-mem -mlarge-mem -mstdmain @gol
+-mfixed-range=@var{register-range}}
+
 @emph{System V Options}
 @gccoptlist{-Qy  -Qn  -YP,@var{paths}  -Ym,@var{dir}}
 
@@ -8081,6 +8088,7 @@
 * Score Options::
 * SH Options::
 * SPARC Options::
+* SPU Options::
 * System V Options::
 * TMS320C3x/C4x Options::
 * V850 Options::
@@ -13616,6 +13624,74 @@
 This is a synonym for @option{-pthreads}.
 @end table
 
+@node SPU Options
+@subsection SPU Options
+@cindex SPU options
+
+These @samp{-m} options are supported on the SPU:
+
+@table @gcctabopt
+@item -mwarn-reloc
+@itemx -merror-reloc
+@opindex mwarn-reloc
+@opindex merror-reloc
+
+The loader for SPU does not handle dynamic relocations.  By default, GCC
+will give an error when it generates code that requires a dynamic
+relocation.  @option{-mno-error-reloc} disables the error,
+@option{-mwarn-reloc} will generate a warning instead.
+
+@item -msafe-dma
+@itemx -munsafe-dma
+@opindex msafe-dma
+@opindex munsafe-dma
+
+Instructions which initiate or test completion of DMA must not be
+reordered with respect to loads and stores of the memory which is being
+accessed.  Users typically address this problem using the volatile
+keyword, but that can lead to inefficient code in places where the
+memory is known to not change.  Rather than mark the memory as volatile
+we treat the DMA instructions as potentially effecting all memory.  With
+@option{-munsafe-dma} users must use the volatile keyword to protect
+memory accesses.
+
+@item -mbranch-hints
+@opindex mbranch-hints
+
+By default, GCC will generate a branch hint instruction to avoid
+pipeline stalls for always taken or probably taken branches.  A hint
+will not be generated closer than 8 instructions away from its branch.
+There is little reason to disable them, except for debugging purposes,
+or to make an object a little bit smaller.
+
+@item -msmall-mem
+@itemx -mlarge-mem
+@opindex msmall-mem
+@opindex mlarge-mem
+
+By default, GCC generates code assuming that addresses are never larger
+than 18 bits.  With @option{-mlarge-mem} code is generated that assumes
+a full 32 bit address.
+
+@item -mstdmain
+@opindex mstdmain
+
+By default, GCC links against startup code that assumes the SPU-style
+main function interface (which has an unconventional parameter list).
+With @option{-mstdmain}, GCC will link your program against startup
+code that assumes a C99-style interface to @code{main}, including a
+local copy of @code{argv} strings.
+
+@item -mfixed-range=@var{register-range}
+@opindex mfixed-range
+Generate code treating the given register range as fixed registers.
+A fixed register is one that the register allocator can not use.  This is
+useful when compiling kernel code.  A register range is specified as
+two registers separated by a dash.  Multiple register ranges can be
+specified separated by a comma.
+
+@end table
+
 @node System V Options
 @subsection Options for System V
 
Index: gcc/doc/contrib.texi
===================================================================
--- gcc/doc/contrib.texi	(revision 39923)
+++ gcc/doc/contrib.texi	(working copy)
@@ -822,6 +822,9 @@
 Andrey Slepuhin for assorted AIX hacking.
 
 @item
+Trevor Smigiel for contributing the SPU port.
+
+@item
 Christopher Smith did the port for Convex machines.
 
 @item
Index: gcc/testsuite/gcc.dg/vect/vect.exp
===================================================================
--- gcc/testsuite/gcc.dg/vect/vect.exp	(revision 39923)
+++ gcc/testsuite/gcc.dg/vect/vect.exp	(working copy)
@@ -52,6 +52,8 @@
 	}
 	set dg-do-what-default compile
     }
+} elseif { [istarget  "spu-*-*"] } {
+   set dg-do-what-default run
 } elseif { [istarget "i?86-*-*"] || [istarget "x86_64-*-*"] } {
     lappend DEFAULT_VECTCFLAGS "-msse2"
     set dg-do-what-default run
Index: gcc/testsuite/gcc.dg/vect/vect-70.c
===================================================================
--- gcc/testsuite/gcc.dg/vect/vect-70.c	(revision 39923)
+++ gcc/testsuite/gcc.dg/vect/vect-70.c	(working copy)
@@ -3,7 +3,7 @@
 #include <stdarg.h>
 #include "tree-vect.h"
 
-#define N 16
+#define N 12
 
 struct s{
   int m;
Index: gcc/testsuite/gcc.dg/vect/fast-math-vect-reduc-7.c
===================================================================
--- gcc/testsuite/gcc.dg/vect/fast-math-vect-reduc-7.c	(revision 39923)
+++ gcc/testsuite/gcc.dg/vect/fast-math-vect-reduc-7.c	(working copy)
@@ -50,5 +50,6 @@
   return 0;
 }
 
-/* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect" } } */
+/* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect" { xfail vect_no_compare_double } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_no_compare_double } } } */
 /* { dg-final { cleanup-tree-dump "vect" } } */
Index: gcc/testsuite/g++.dg/vect/vect.exp
===================================================================
--- gcc/testsuite/g++.dg/vect/vect.exp	(revision 39923)
+++ gcc/testsuite/g++.dg/vect/vect.exp	(working copy)
@@ -61,6 +61,8 @@
         }
         set dg-do-what-default compile
     }
+} elseif { [istarget  "spu-*-*"] } {
+   set dg-do-what-default run
 } elseif { [istarget "i?86-*-*"] || [istarget "x86_64-*-*"] } {
     lappend DEFAULT_VECTCFLAGS "-msse2"
     set dg-do-what-default run
Index: gcc/testsuite/lib/target-supports.exp
===================================================================
--- gcc/testsuite/lib/target-supports.exp	(revision 39923)
+++ gcc/testsuite/lib/target-supports.exp	(working copy)
@@ -1255,6 +1255,7 @@
 	set et_vect_int_saved 0
 	if { [istarget i?86-*-*]
 	      || [istarget powerpc*-*-*]
+	      || [istarget spu-*-*]
 	      || [istarget x86_64-*-*]
 	      || [istarget sparc*-*-*]
 	      || [istarget alpha*-*-*]
@@ -1436,6 +1437,7 @@
 	set et_vect_float_saved 0
 	if { [istarget i?86-*-*]
 	      || [istarget powerpc*-*-*]
+	      || [istarget spu-*-*]
 	      || [istarget mipsisa64*-*-*]
 	      || [istarget x86_64-*-*]
 	      || [istarget ia64-*-*] } {
@@ -1459,7 +1461,8 @@
     } else {
 	set et_vect_double_saved 0
 	if { [istarget i?86-*-*]
-	      || [istarget x86_64-*-*] } {
+	      || [istarget x86_64-*-*] 
+	      || [istarget spu-*-*] } {
 	   set et_vect_double_saved 1
 	}
     }
@@ -1468,6 +1471,26 @@
     return $et_vect_double_saved
 }
 
+# Return 0 if the target supports hardware comparison of vectors of double, 0 otherwise.
+#
+# This won't change for different subtargets so cache the result.
+
+proc check_effective_target_vect_no_compare_double { } {
+    global et_vect_no_compare_double_saved
+
+    if [info exists et_vect_no_compare_double_saved] {
+        verbose "check_effective_target_vect_no_compare_double: using cached result" 2
+    } else {
+        set et_vect_no_compare_double_saved 0
+        if { [istarget spu-*-*] } {
+           set et_vect_no_compare_double_saved 1
+        }
+    }
+
+    verbose "check_effective_target_vect_no_compare_double: returning $et_vect_no_compare_double_saved" 2
+    return $et_vect_no_compare_double_saved
+}
+
 # Return 1 if the target plus current options does not support a vector
 # max instruction on "int", 0 otherwise.
 #
@@ -1481,6 +1504,7 @@
     } else {
 	set et_vect_no_int_max_saved 0
 	if { [istarget sparc*-*-*]
+	     || [istarget spu-*-*]
 	     || [istarget alpha*-*-*] } {
 	    set et_vect_no_int_max_saved 1
 	}
Index: gcc/config.gcc
===================================================================
--- gcc/config.gcc	(revision 39923)
+++ gcc/config.gcc	(working copy)
@@ -334,6 +334,10 @@
 sparc*-*-*)
 	cpu_type=sparc
 	;;
+spu*-*-*)
+	cpu_type=spu
+	need_64bit_hwint=yes
+	;;
 s390*-*-*)
 	cpu_type=s390
 	need_64bit_hwint=yes
@@ -2327,6 +2331,14 @@
 	extra_options="${extra_options} sparc/long-double-switch.opt"
 	tmake_file="${tmake_file} sparc/t-netbsd64"
 	;;
+spu-*-elf*)
+	tm_file="dbxelf.h elfos.h spu/spu-elf.h spu/spu.h"
+	tmake_file="spu/t-spu-elf"
+	extra_headers="spu_intrinsics.h spu_internals.h vmx2spu.h spu_mfcio.h vec_types.h"
+	extra_modes=spu/spu-modes.def
+	c_target_objs="${c_target_objs} spu-c.o"
+	cxx_target_objs="${cxx_target_objs} spu-c.o"
+	;;
 strongarm-*-elf*)
 	tm_file="arm/strongarm-elf.h dbxelf.h elfos.h arm/unknown-elf.h arm/elf.h arm/aout.h arm/arm.h"
 	tmake_file="arm/t-arm arm/t-strongarm-elf"
Index: libcpp/configure
===================================================================
--- libcpp/configure	(revision 39923)
+++ libcpp/configure	(working copy)
@@ -8245,6 +8245,7 @@
 	sparc64*-*-* | ultrasparc-*-freebsd* | \
 	sparcv9-*-solaris2* | \
 	sparc-*-solaris2.[789] | sparc-*-solaris2.1[0-9]* | \
+	spu-*-* | \
 	sh[123456789l]*-*-*)
 		need_64bit_hwint=yes ;;
 	*)
Index: libcpp/configure.ac
===================================================================
--- libcpp/configure.ac	(revision 39923)
+++ libcpp/configure.ac	(working copy)
@@ -128,6 +128,7 @@
 	sparc64*-*-* | ultrasparc-*-freebsd* | \
 	sparcv9-*-solaris2* | \
 	sparc-*-solaris2.[789] | sparc-*-solaris2.1[0-9]* | \
+	spu-*-* | \
 	sh[123456789l]*-*-*)
 		need_64bit_hwint=yes ;;
 	*)
