[llvm-dev] Question about RISCV gp-relaxtion

[Fangrui Song via llvm-dev]

On 2021-10-19, Shiva Chen via llvm-dev wrote:
>Hi,
>
>To my understanding, lwgp/swgp might need linker relaxation because linker
>can resolve the symbol address and determine whether the gp-offset fit in
>to the instructions.

I am always of the opinion that if global variable load/store
has been a performance/code size bottleneck, the application
author needs to think why.

Even 64kb range is pretty limited.
It may appear that adding such an instruction can decrease code size for
some use cases or perhaps benchmarks specifically written for them, but
I wonder whether it would be a good use of an opcode.

>There are linker relaxation patches on lld but didn't land yet.
>https://reviews.llvm.org/D77694
>https://reviews.llvm.org/D100835
>
>Hope this helps,
>Shiva
>
>
>liao <liaochunyu126 at 126.com> 於 2021年10月18日 週一 上午10:08寫道：
>
>> CC
>>
>>
>>
>> At 2021-10-15 15:01:30, "liao" <liaochunyu126 at 126.com> wrote:
>>
>> Maybe the LLD doesn't support linker relaxtion (It is difficult to
>> implement).
>> (Correct me if I'm wrong)
>>
>> I want to implement lwgp, 17-bit/128KB gp-offset. (
>> https://github.com/riscv/riscv-code-size-reduction/blob/after_v0.50.1_dev/ISA%20proposals/Huawei/Zce_spec.adoc#lwgp_semantics
>> )
>>
>> Eg:  lui a0, %hi(sym); load/store a1, %lo(sym)(a0) -> lwgp/swgp a1,
>> gp_offset(gp)
>>
>>
>> question:
>>
>> 1. Do I have to support linker relaxtion if I want to implement lwgp?
>>
>> 2. Is there any other way to solve the problem？ assmembler?
>>
>>
>>
>>
>>
>>
>>
>>
>>

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