[llvm-dev] [llvm-mca] Resource consumption of ProcResGroups

[Alex Renda via llvm-dev]

Hi,

I’m trying to work out the behavior of llvm-mca on instructions with ProcResGroups. My current understanding is:

When an instruction requests a port group (e.g., HWPort015) and all of its atomic sub-resources (e.g., HWPort0,HWPort1,HWPort5), HWPort015 is marked as “reserved” and is issued in parallel with HWPort0, HWPort1, and HWPort5, blocking future instructions from reserving HWPort015 for the duration but not explicitly blocking any of HWPort0, HWPort1, or HWPort5 (although those ports are in fact blocked because the instruction also requested usage of those ports).

When an instruction requests a port group (e.g., HWPort015) but only some of its atomic sub-resources (e.g., HWPort0 and HWPort1 but not HWPort5), then HWPort015 is scheduled according to the round robin scheduler, which in this case would decide to dispatch it on Port5.

This (I believe) explains the following reported timings on a basic block which consists of a single instruction with no dependencies and a small NumMicroOps (i.e., only bottlenecked by resource availability), where I have tried out different port maps and ResourceCycles (all of these are for 100 iterations):

• When the resource mapping is: { HWPort0: 2 cycles, HWPort01: 2 cycles }, the instruction has a Total Cycles of 200, because the round-robin scheduler always assigns the HWPort01 resource to execute on HWPort1, so each iteration requires 2 cycles total.
• When the resource mapping is: { HWPort0: 2 cycles, HWPort1: 2 cycles, HWPort01: 2 cycles }, the instruction still has a Total Cycles of 200, because HWPort01 is marked as “reserved” and therefore issued in parallel to HWPort0 and HWPort1, so each iteration still requires 2 cycles total.


The one case that still confuses me is:

• When the resource mapping is: { HWPort0: 2 cycles, HWPort01: 4 cycles }, the instruction has a Total Cycles of 300. This seems to be because issuing to HWPort01 does not always block when I intuitively think it should (e.g., instructions are issued on Cycle 1, Cycle 3 (?), Cycle 7, Cycle 9 (?), and so on, where (?) indicates that I don’t think it should be possible to issue then, but it does anyway).



Is this understanding of llvm-mca’s behavior correct? Are these observations intentional design decisions, limitations of llvm-mca’s model, bugs, or something else?

Thanks!
-Alex
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