[llvm-dev] How to add new AVR targets?
Wilhelm Meier via llvm-dev
llvm-dev at lists.llvm.org
Mon Mar 30 12:00:38 PDT 2020
Hi Dylan,
I used the following commandline:
clang++ -Os -DF_OSC=20000000 -DF_CPU=20000000 --target=avr -I.
-I../include0 -I../../include0 -I../../../include0 -I../../include0/std
-I../include0/std -I../../../include0/std -I../../3rdparty/boost
-I/usr/avr/include -mmcu=atmega328p
/home/lmeier/Projekte/wmucpp/clang/bm00/bm00.cc -S -emit-llvm --output
bm00.ir
Please find the IR attached in the file bm00.ir
Thanks,
Wilhelm
Am 30.03.20 um 13:44 schrieb Dylan McKay:
> Hey Wilhelm,
>
> Could you post the LLVM IR generated from your C++ file?
>
> This can be achieved with 'clang -S -emit-llvm'
>
> Cheers
>
> On Sat, Mar 28, 2020 at 6:36 PM Wilhelm Meier <wilhelm.meier at hs-kl.de
> <mailto:wilhelm.meier at hs-kl.de>> wrote:
>
> Answering partly to myself there was a extern "C" missing.
>
> But the register pushes ans reti are still missing.
>
> Whats wrong?
>
> Am 28.03.20 um 06:26 schrieb Wilhelm Meier via llvm-dev:
> > Hi Dylan,
> >
> > the following code
> >
> > volatile uint8_t v1;
> > volatile uint8_t v2;
> >
> > __attribute__((interrupt)) void __vector_21(void) {
> > v2 = v1;
> > }
> >
> > produces in C mode:
> >
> > 00000092 <__vector_21>:
> > 92: 80 91 61 00 lds r24, 0x0061 ; 0x800061 <v1>
> > 96: 80 93 60 00 sts 0x0060, r24 ; 0x800060 <__data_end>
> > 9a: 08 95 ret
> >
> > and in C++ mode:
> >
> > 00000074 <_Z11__vector_21v>:
> > 74: 80 91 60 00 lds r24, 0x0060 ; 0x800060 <__data_end>
> > 78: 80 93 61 00 sts 0x0061, r24 ; 0x800061 <v2>
> > 7c: 08 95 ret
> >
> > So, in C++ mode it is not recognized as ISR due to name mangling.
> >
> > Furthermore there are no register push/pos and no reti.
> >
> > Whats wrong?
> >
> > Thanks.
> >
> >
> > Am 11.03.20 um 08:13 schrieb Dylan McKay:
> >> Here you go Wilhelm,
> >>
> >> https://github.com/dylanmckay/clang-avr-libc-interrupt-example
> >>
> >>
> >>
> >> On Thu, Mar 5, 2020 at 4:05 AM Wilhelm Meier
> <wilhelm.meier at hs-kl.de <mailto:wilhelm.meier at hs-kl.de>
> >> <mailto:wilhelm.meier at hs-kl.de <mailto:wilhelm.meier at hs-kl.de>>>
> wrote:
> >>
> >> Am 04.03.20 um 13:28 schrieb Dylan McKay:
> >>
> >> >
> >> > * *The C/C++ function needs to be declared with either
> the calling
> >> > convention avr-interrupt or
> avr-non-blocking-interrupt.* Skipping
> >> > this step will cause regular ret instructions to be
> emitted for
> >> > return-from-subroutine, instead of the required reti
> for interrupt
> >> > handlers. ISRs also have stricter requirements on which
> registers
> >> > must not be clobbered after execution, which the
> backend will
> >> handle
> >> > properly by restoring all clobbered registers in the
> interrupt
> >> > handler epilogue
> >> > * *The symbol names of the ISR function handlers must
> match those
> >> > referred to in avr-libc/avr-libgcc/crt*. This is
> because the ISR
> >> > table is specified in assembly inside the GCC AVR CRT.
> The way it
> >> > works is that the external symbol references in the CRT
> object
> >> files
> >> > are declared with an exotic linkage type that causes
> the linker to
> >> > skip linking of the symbols if they are undefined
> references.
> >> If you
> >> > chose a custom ISR table in a custom CRT or runtime
> library, you
> >> > would be free to choose ISR names as you pleased.
> >> >
> >> Thank you for your explanation. But I suspect I didn't get it
> right. Can
> >> you please provide an example?
> >>
> >> Thanks
> >>
> > _______________________________________________
> > LLVM Developers mailing list
> > llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>
> > https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
> >
>
-------------- next part --------------
; ModuleID = '/home/lmeier/Projekte/wmucpp/clang/bm00/bm00.cc'
source_filename = "/home/lmeier/Projekte/wmucpp/clang/bm00/bm00.cc"
target datalayout = "e-P1-p:16:8-i8:8-i16:8-i32:8-i64:8-f32:8-f64:8-n8-a:8"
target triple = "avr"
@v1 = dso_local global i8 0, align 1
@v2 = dso_local global i8 0, align 1
; Function Attrs: norecurse noreturn nounwind optsize
define dso_local i16 @main() local_unnamed_addr addrspace(1) #0 {
entry:
tail call addrspace(0) void asm sideeffect "sei", "~{memory}"() #2, !srcloc !2
br label %while.body
while.body: ; preds = %entry, %while.body
%0 = load volatile i8, i8* @v2, align 1, !tbaa !3
store volatile i8 %0, i8* @v1, align 1, !tbaa !3
br label %while.body
}
; Function Attrs: nofree norecurse nounwind optsize
define dso_local void @__vector_21() local_unnamed_addr addrspace(1) #1 {
entry:
%0 = load volatile i8, i8* @v1, align 1, !tbaa !3
store volatile i8 %0, i8* @v2, align 1, !tbaa !3
ret void
}
attributes #0 = { norecurse noreturn nounwind optsize "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="atmega328p" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nofree norecurse nounwind optsize "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "interrupt" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="atmega328p" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #2 = { nounwind }
!llvm.module.flags = !{!0}
!llvm.ident = !{!1}
!0 = !{i32 1, !"wchar_size", i32 2}
!1 = !{!"clang version 11.0.0 (https://github.com/llvm/llvm-project.git 05f0e598ab265a80fedb23225cde4176f11774ac)"}
!2 = !{i32 -2147258750}
!3 = !{!4, !4, i64 0}
!4 = !{!"omnipotent char", !5, i64 0}
!5 = !{!"Simple C++ TBAA"}
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