[llvm-dev] Questions on ifconversion and predication

[Bagel via llvm-dev]

Assume an architecture that has multiple condition code registers, e.g., powerpc.

Now assume that there are predicate instructions like thumb2, but can specify
which condition code register they refer to.

Now also assume that these predicate instructions themselves are predicatible,
if executed they change the current predication state.

Can LLVM handle multiple levels of predication?
When is IfConversion used and when is EarlyIfConversion used?
Is there any documentation on this?

thanks,
brian