[llvm-dev] Questions about vscale

[Renato Golin via llvm-dev]

On Wed, 8 Apr 2020 at 04:23, Kai Wang <kai.wang at sifive.com> wrote:
> If we apply the type system pointed out by Renato, is the vector type <vscale x 1 x i16> legal? If we decide that <vscale x 1 x i16> is a fundamentally impossible type, does it contrary to the philosophy of LLVM IR as reasonably target-independent IR? I do not get the point of your argument.

Hi Kai,

Don't worry about target-independent IR in your design of intermediate
passes or lowering.

By the time the front-end lowers to LLVM IR, it already has, often
irreversible, target-specific knowledge in it.

If by some stroke of luck that doesn't happen, then using "<vscale x
anything>" is enough indication that you should not try to lower that
onto a target that it wasn't specifically aimed at.

No one expects the middle-end to be target-neutral. That's the whole
point of constantly asking target-specific machinery (like TTI) about
what's possible or what's "good" and what's not.

More importantly, the closer you are to the end of the pass pipeline,
the closer the IR is to machine IR. It's not uncommon, and often
expected, to see "just the right amount of shuffles" to match lowering
patterns into MIR and then Asm.

IIRC, OpenCL or some other parallel-compute/graphic oriented pipeline
does use odd vector shapes and legalise them later on.

I may be severely outdated in my opinion, and happy to be corrected,
but I don't think it would be totally egregious to carry on with
(whole numbered) vector shapes that aren't strictly legal, as long as
you guarantee that *any* such pattern gets correctly legalised by the
lowering.

If you can make the adversarial cases performing on top of that, it's
a bonus, not a target.

Hope this helps.

cheers,
--renato