[llvm-dev] Matching the same chain multiple times?

[Thomas Lively via llvm-dev]

Hi all!

I'm trying to do instruction selection on a pattern like the following:

Pat<(v4i32 (build_vector (i32 (load I32:$addr)), (i32 (load I32:$addr)),
(i32 (load I32:$addr)), (i32 (load I32:$addr))))), (LOAD_SPLAT 0, 0,
I32:$addr)>;

Note that all those loads are actually the same load. This fails to match
as expected because of the OPC_EmitMergeInputChains operation. There is a
check at
https://github.com/llvm/llvm-project/blob/20b52c33ba3960340ecf326314517091b8ec98f4/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp#L3304
that
the chain to be merged has only one use, but in this case it has four uses,
all of which are matched in the same pattern.

I've tried updating the condition to allow this, but I haven't had any luck
so far. Is there any other way to perform the match I want?
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