[llvm-dev] x86 instructions EFLAGS in TableGen

Craig Topper via llvm-dev llvm-dev at lists.llvm.org
Mon Jun 24 20:45:49 PDT 2019

We don’t model the eflags at that level. With maybe the exception of the
direction flag. It’s just not that useful to the compiler to have the exact
bits that are changed. And I’m not even sure we would ever emit CLC on our

On Mon, Jun 24, 2019 at 7:59 PM Antonin Reitz via llvm-dev <
llvm-dev at lists.llvm.org> wrote:

> Hello,
> Here is one question regarding the LLVM TableGen:
> Which file in the llvm/lib/Target/X86 folder describes how the bits in
> the EFLAGS register are modified by the x86 instructions? For example,
> in the "X86InstrInfo.td" file, lines 2134-2135, it says:
> let SchedRW = [WriteALU], Defs = [EFLAGS], Uses = [EFLAGS] in {
> def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
> So it says the Defs of CLC is EFLAGS, but actually the CLC instruction
> only clears the "CF" flag in the EFLAGS register and has nothing to do
> with the other bits of EFLAGS. So which files in this folder describes
> the fact that CLC only modifies the CF bit?
> Thank you in advance,
> Antonin Reitz
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