[llvm-dev] empty list assertion

[Krzysztof Parzyszek via llvm-dev]

On 1/10/2019 10:38 PM, m m wrote:
> 
> Sorry I'm new to LLVM and not sure what a 'value type' is.
> I have 2 register classes and they are defined like this:
> 
> def CPURegs : RegisterClass<"ABC", [i32], 32, (add R0, R1, R3, R4)>;
> 
> def CFRegs : RegisterClass<"ABC", [i1], 8, (add CF)>
> {
>          let isAllocatable = 0;
>          let Size = 8;
> }
> 

By "value type" I meant "MachineValueType", which is a low-level 
representation of a type. It's easier to understand what it is by simply 
looking in MachineValueType.h: these are things like i8 or i32 
(representing 8- and 32-bit integers), or f32 (for 32-bit floating 
point), etc.

Each definition of a register class will have a set of value types that 
registers from that class can hold. This set will be used in the 
instruction selection to pick an appropriate register to hold a value of 
a given type. It seems like in your case the value type lists are there, 
so the assertion is likely coming from somewhere else. On that note, you 
seem to be using a very old version of LLVM. Do you have a reason for 
that? If not, try updating the LLVM sources---many things have changed 
since then, including parts of LLVM that are related to the problem 
you're seeing. I don't know if the problem would go away, but it would 
be easier for you to get help with it, if it's still present.

-Krzysztof


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