[llvm-dev] Question about 'outs' and 'PredicateOperand' on TableGen

JinGu Kang via llvm-dev llvm-dev at lists.llvm.org
Thu Aug 15 08:03:27 PDT 2019

Hi All,

I have a question about 'outs' and 'PredicateOperand' on TableGen. Let's see simple TableGen example.

def pred : PredicateOperand<OtherVT, (ops ..)>;

def test_cmp : TestInst<(outs pred:$dst0), ... >;

Above definitions cause TableGen crash. It seems below code causes the crash.

On utils/TableGen/CodeGenDAGPatterns.cpp

static unsigned GetNumNodeResults(Record *Operator, CodeGenDAGPatterns &CDP) {
    // Subtract any defaulted outputs.
    for (unsigned i = 0; i != InstInfo.Operands.NumDefs; ++i) {
      Record *OperandNode = InstInfo.Operands[i].Rec;

       if (OperandNode->isSubClassOf("OperandWithDefaultOps") &&   ==> I think it checks 'PredicateOperand'.

>From above code, I guess we can not use 'PredicateOperand' on 'outs'. Is it one of TableGen's rule? I was not able to find the related rules... In my case, the output of compare instruction is in predicate register rather than status register and it is used for predication of instructions. If anyone knows about it or I missed something, please let me know.


JinGu Kang
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