[llvm-dev] Can I use AArch64 Opcodes inside MachineCSE Pass
Ramakota Reddy via llvm-dev
llvm-dev at lists.llvm.org
Wed Apr 10 03:45:10 PDT 2019
I have Instruction like below
%9:gpr32 = ADDWrr killed %7:gpr32, killed %4:gpr32
Here I want to check Opcode of above instruction in MachineCSE pass. But ADDWrr is a AArch64 Opcode.
How can I use/check AArch64 Opcodes in MachineCSE pass(like: Inst->Opcode() == AArch64::ADDWrr) ?. through any object can I use AArch64 Opcodes ?
Can I use AArch64 Opcodes inside MachineCSE Pass?
Could anyone please give your suggestions on this problem.
Thanks & Regards,
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