[llvm-dev] Please expose predicates to MachineVerifier

Mark Schimmel via llvm-dev llvm-dev at lists.llvm.org
Mon Apr 1 11:20:32 PDT 2019

Could we expose predicates defined in the target InstrInfo.td file to the MachineVerifier? We use BuildMI() to create many instructions after ISEL, but the predicates are not being checked at this point. Thus, I could forget to check the target and build an instruction that is illegal for a specific configuration. In such a case it would be nice if the MachineVerifier could detect this for me.

Example predicate IsCore8 usage:

def ADDx: BINOP<...>, Requires<[IsCore8]>;

let Predicates=[IsCore8] in {
def : SUBX: BINOP<...>;

The predicates are encoded into the targets GenDAGIsel file but not anywhere else that I can find:
  OPC_CheckPatternPredicate, 4, // (Subtarget.isCore8())


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