[llvm-dev] [MIPS] MIPS 1 EI/DI instruction regression since 3.9

[Dan Ravensloft via llvm-dev]

Indeed, this appears to be a documentation issue in the EE instruction set
manual; it's an EE specific opcode (EI is 0x42000038, DI is 0x42000039)
mislabelled as being MIPS I, when that was never defined before MIPS32r2.

My mistake, sorry about that.

On Mon, 29 Oct 2018 at 17:25, Daniel Sanders <daniel_l_sanders at apple.com>
wrote:

>
>
> On Oct 27, 2018, at 06:42, Dan Ravensloft via llvm-dev <
> llvm-dev at lists.llvm.org> wrote:
>
> So, I have been working on Clang for the PS2, and recently decided a
> different approach of pretending the very quirky EE is a MIPS II CPU.
>
> During this process, I found that Clang refused to compile some assembly
> code with the MIPS instructions ei and di (enable/disable interrupts):
>
> src/glue.c:32:17: error: instruction requires a CPU feature not currently
> enabled
>                 asm volatile ("di");
>                               ^
>
> Though I haven't bisected it in full, judging by this Godbolt (
> https://godbolt.org/z/iRVpzd), these instructions have been
> feature-locked (incorrectly, as it is a MIPS 1 instruction) ever since
> Clang 3.9 (3.8.x works okay). It's worth noting that the instructions work
> fine with MIPS32r2 and above.
>
>
> It's been a while but that's probably around the point I went through the
> instructions and made sure MIPS II - V worked correctly in the assembler
> and verified the behaviour against GNU AS using the available documentation
> and llvm-mc-disassembler-fuzzer to generate test cases. Before that, there
> was no MIPS II - V support in LLVM. MIPS I was excluded since there's no
> known usage of that ISA.
>
> The architecture docs (
> https://www.mips.com/products/architectures/mips32-2/) say it was added
> in MIPS32r2. If it was defined before then then it's odd that that document
> doesn't define it for MIPS32r1. MIPS didn't have any of pre MIPS32 docs
> available so the earliest docs I could find at the time was for MIPS II -
> IV (
> https://www.cs.cmu.edu/afs/cs/academic/class/15740-f97/public/doc/mips-isa.pdf)
> which doesn't mention ei/di. Additionally, they're COP0 instructions and
> it's mentioned at https://en.wikipedia.org/wiki/MIPS_architecture that
> COP0 is implementation defined for MIPS I - V. That being the case, ei/di
> for EE may be different from the MIPS32r2 one and should probably enabled
> for EE specifically rather than for MIPS II - V.
>
> I will try to bisect and possibly fix this bug.
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>
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