[llvm-dev] [RFC] Array Register Files

Luke Kenneth Casson Leighton via llvm-dev llvm-dev at lists.llvm.org
Tue Oct 9 04:54:32 PDT 2018


On Tue, Oct 9, 2018 at 11:30 AM Robin Kruppe <robin.kruppe at gmail.com> wrote:
>
> On Tue, 9 Oct 2018 at 04:03, Luke Kenneth Casson Leighton via llvm-dev
> <llvm-dev at lists.llvm.org> wrote:

> > (4) VL ties in with robin kruppe's intermediary representation RFC
> > (initially designed for RVV). i think it's important to get in touch
> > with him on that.
>
> Luke, I've been hesitant to reply to you here because I wanted to
> write a more helpful explanation than I managed below, but since you
> name dropped me and this subthread is getting larger and larger, I'll
> just go ahead and say: I don't know what you are talking about
> whenever you mention RVV in this context.

 yes, apologies (not a problem, robin. btw, i really appreciate the
way you worded this, it's very respectful): i worked that out last
night... and, because i'd written 2 messages already i did not want to
say anything further until someone else responded.  sorry to take up
your time.

 so, apologies!  the RFC that you wrote, robin, is not relevant for
combining with this one as far as RVV is concerned [it is however
extremely relevant for SV].

it was only this morning that i suddenly realised that the ARF RFC
actually has more in common with SIMD than with RVV (or any of the
other vector unit engine developers that i privately bcc'd).

 in particular, the ARF RFC would be *really* useful to deal with the
horrible-ness of that x86 MMX/SSE extension, the one that overloaded
the floating-point register file as SIMD *integer* elements?

 in that regard, nicolai (et al, at AMD) it may be worthwhile alerting
some colleagues at AMD, if there are any who work on LLVM for amd64,
see if they are interested to participate?

l.


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