[llvm-dev] ARM64, dropping ADRP instructions, and ld.lld

[Peter Smith via llvm-dev]

Ok, thanks for the clarification that makes sense.

Peter

On 21 May 2018 at 15:03, Tim Northover <t.p.northover at gmail.com> wrote:
> On 21 May 2018 at 14:52, Peter Smith <peter.smith at linaro.org> wrote:
>> The resulting code section is 4 byte aligned, I'm not sure where the
>> requirement for 4k aligned sections come from unless you are planning
>> to use ADRP alone?
>
> I think it's the segments that need to be 4K aligned (i.e. after
> linking). Normally this isn't really an extra constraint because
> you're just going to map them in with the MMU anyway, but in strange
> embedded situations I could see it being a problem.
>
> Consider the fully linked sequence:
>
>     adrp x0, #0
>     add x0, x0, #8
>
> Starting at 0x1000 this would result in x0 == 0x1008 == pc, at 0x1ffc
> it would result in x0 == 0x1008 != pc. Not good for
> position-independence (or static positioning, but for different
> reasons not illustrated by that example).
>
> Cheers.
>
> Tim.