[llvm-dev] RFC: [SLP] Vectorize bit-parallel operations using general purpose registers.
Clement Courbet via llvm-dev
llvm-dev at lists.llvm.org
Thu Jun 28 08:23:58 PDT 2018
I'd like to get people's opinions about a small change extending SLP to
handle vectorization of some instructions using general purpose registers.
A description of the issue and a proof of concept can be found here:
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