[llvm-dev] LLVM Scheduler Target Description

ComputerFreak via llvm-dev llvm-dev at lists.llvm.org
Wed Jun 27 18:23:38 PDT 2018


hi, Recently working on LLVM Target Scheduler Target Description file, I have a question on InstrStage Class.
As shown on Scheduler Tutorial, it says  
 
"/// { 2, x|y, 1 }
 /// indicates that the stage occupies either FU x or FU y for 2
 /// consecutive cycles and that the next stage starts one cycle
 /// after this stage starts. That is, the stage requirements
 /// overlap in time."

‚ÄčIf I understood right, this mean that this instruction takes 2 cycles to complete.
After first cycle passes, the another instruction (which has same InstrItinClass name) can be in this stage.  
 
My questions are:  
1. Am I understanding in right way?
 
2. What does the FuncUnit means in this case? Does this mean a module such as ALU, FPU?  
 
3. when I set third operand as 0, this mean the instruction can start simultaneously?  
 
P.S. Always thanks  LLVM Community  for giving warm kind knowledge.  
 
 
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