[llvm-dev] Target hardware loop instruction via intrinsics
Hal Finkel via llvm-dev
llvm-dev at lists.llvm.org
Thu Jun 21 11:25:09 PDT 2018
On 06/21/2018 01:07 PM, Jon Chesterfield via llvm-dev wrote:
> Hexagon has a MIR pass for detecting loops that map onto hardware
> support. I think a similar approach would be viable for my target but
> am put off by the complexity of determining whether a given loop is
> legal to transform.
I think that it is easier to do this legality checking at the IR level
(where we can take advantage of the ScalarEvolution analysis). This is
what PowerPC does (see lib/Target/PowerPC/PPCCTRLoops.cpp). I recommend
that you take this approach if possible.
> Instead, I would like to pass the responsibility for determining
> legality onto the C programmer who is assumed sufficiently familiar
> with the architecture.
> I think this would require a pair of intrinsics to denote the start
> and end of the loop. Is there a reasonable way to model this in llvm?
> If not, would anyone suggest a compiler programmer friendly, even if
> application programmer hostile, way to target a loop instruction with
> many constraints on validity.
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
Lead, Compiler Technology and Programming Languages
Leadership Computing Facility
Argonne National Laboratory
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