[llvm-dev] [VLIW Scheduler] Itineraries vs. per operand scheduling

Krzysztof Parzyszek via llvm-dev llvm-dev at lists.llvm.org
Thu Feb 8 11:40:22 PST 2018

We have a two different dimensions for each instruction: slot 
assignments, and operand timings. These two are unrelated to each other, 
and also each (or both) can change for any given instruction from one 
architecture version to the next.

The main concern for us was which of these mechanisms contains all the 
information that we need. We cannot express all the scheduling details 
by hand, and majority of it was auto-generated anyway. I don't know if 
the new model has all the required pieces of information, but we've been 
using itineraries for a while, and we stuck with them.

The short answer is "because it works", but it's not meant to imply that 
nothing else would.


On 2/8/2018 8:49 AM, 陳韋任 wrote:
> Hi Krzysztof,
> 2018-02-08 13:32 GMT+08:00 Andrew Trick via llvm-dev 
> <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>>:
>>     On Feb 4, 2018, at 9:15 AM, Yatsina, Marina via llvm-dev
>>     <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote:
>>     Hi,____
>>     __ __
>>     What is the best way to model a scheduler for a VLIW in-order
>>     architecture?____
>>     I’ve looked at the Hexagon and R600 architectures and they are
>>     using itineraries. I wanted to understand the benefit in using
>>     itineraries over the per operand scheduling.
> ​Do you have time to give comment on why Hexagon still use itineraries, 
> rather than switching to per operand scheduling like ARM does? I really 
> like to hear your opinion.
> Thanks.​ :-)
> -- 
> Wei-Ren Chen (陳韋任)
> Homepage: https://people.cs.nctu.edu.tw/~chenwj

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