[llvm-dev] Tablegen: frameindex matches register
Gleb Popov via llvm-dev
llvm-dev at lists.llvm.org
Sun Dec 23 22:18:24 PST 2018
In my backend I have following definition:
def StoreStackR : MyInst<2, (outs), (ins IntRegs:$addr, IntRegs:$reg),
"store $reg, [$addr]", [(store i32:$reg,
However, LLVM generates both
storestackr %reg1, [%reg2]
storestackr %reg1, 
using this definition. I was expecting that "IntRegs:$addr" would constrain
it to registers only. As consequence, I can't infer operand type from the
opcode. What's the proper way to solve this?
Thanks in advance.
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