[llvm-dev] Branch relaxation at assembler level (RISCV)
Paolo via llvm-dev
llvm-dev at lists.llvm.org
Tue Dec 4 13:17:36 PST 2018
On 04/12/18 21:13, Friedman, Eli wrote:
> On 12/3/2018 2:45 PM, Paolo via llvm-dev wrote:
>> Hi all,
>> I'm trying to implement the same branch relaxation mechanism implemented
>> in CodeGen in the MC layer of RISCV.
>> beqz t1, L1
>> bnez t1, L2
>> j L1
>> That's because LLVM does not apply the CodeGen optimizations when
>> compiling directly from assembly code.
>> What I'd like to do would be to add a pass that does that on the MC
>> instructions or at least to find a way to implement this relaxation in
>> the MC assembler.
>> Any suggestions on where/how to do it? Or any existing fixes?
> The RISCV assembler already has code for similar transforms; see
> RISCVAsmBackend::mayNeedRelaxation and
> RISCVAsmBackend::relaxInstruction. The only tricky bit is that the
> relaxation interface doesn't expect one instruction to be relaxed to
> two instructions... probably not too hard to change, though, if
> That said, I'm a little skeptical this is actually a good idea; the
> more "smart" the assembler is, the harder it becomes to understand
> what it's doing. No other in-tree target does this sort of transform.
Thank you Eli for the quick reply,
Well, I had seen the RISCVAsmBackend and yes, I agree it wouldn't be a
good idea to make it handle this niche issue.
We thought that we might work at the MC emission level and see what we
can do there.
More information about the llvm-dev