[llvm-dev] Live Register Spilling

[Song, Ruiling via llvm-dev]

From: qcolombet at apple.com [mailto:qcolombet at apple.com]
Sent: Friday, September 15, 2017 1:32 AM
To: jin chuan see <jinchuansee at hotmail.com>
Cc: Song, Ruiling <ruiling.song at intel.com>; Matthias Braun <mbraun at apple.com>; llvm-dev at lists.llvm.org
Subject: Re: [llvm-dev] Live Register Spilling


On Sep 13, 2017, at 9:03 PM, jin chuan see via llvm-dev <llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>> wrote:

Hi All,

Thanks for the reply. I managed to identify and fixed a few errors in my implementation.

However, there are a few errors that i am not sure what is it indicating.
For starters, i think i should explain what i am trying to achieve.

I am actually working on MIPS backend to generate smaller set of MIPS Instructions compared to its existing supported instructions.
Currently, i am working on shifting instructions.

Take an example:
A typical mips sllv syntax goes in this manner:

         sllv $reg1,$reg2,$reg3

The $reg3 contains the shifting amount. Only the LSB 5 bit will be used.
The $reg2 contains the data to be shifted.
The $reg1 contains the data after shifting is performed.

What i want to achieve is to expand sllv instruction to the following routine:

                 andi $reg3,$reg3,0x1f         //To mask the 5 bit LSB shifting amount
#BB_1:    beq  $reg3,$zero,#BB_2    //Branch out from basic block if shifting amount is zero
                 sub  $reg3,$reg3,1              //To subtract 1 from the shifting amount
                 sll  $reg2,$reg2,1                //Shift by 1 bit
                 j    #BB_1                              //Branch back to the begining of the routine
#BB_2:    addu $reg1,$reg2,$zero    //Transfer the completed shift data to the original destination register

Since you guys mentioned that the MI are represented in MachineSSA form, i imagined my routine represented by virtual registers would look something like this:

                andi $vreg3,$vreg3,0x1f
#BB_1:   beq  $vreg3,$zero,#BB_2
                sub  $vreg3,$vreg3,1
                sll  $vreg2,$vreg2,1
                j    #BB_1
#BB_2:  addu $vreg1,$vreg2,$zero

Hi Chuan,

In your example, you should not try to define $vreg3 many times. In SSA form, each value should be defined only once.
You need to create some  new virtual registers and make sure each virtual register will be defined only once.
In your example you may need PHI node. Which is an important concept in SSA. You may need to google it to teach yourself on this.
And you should not insert normal arithmetic instructions between two branch/jump instructions. In your example, there are sub/sll between beq/j. which is invalid.
A ‘basic block’ should only terminate(br/jump) at the last one or two instructions.
llc has many useful options besides verify instructions. It also support printing machine IR before/after each pass which is also very useful. Try ‘llc --help’

Ruiling
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