[llvm-dev] Conditional includes in TableGen?

David Chisnall via llvm-dev llvm-dev at lists.llvm.org
Mon Nov 6 05:50:30 PST 2017

Hello the list,

We have just moved things over to using the new multiple register size things, but this is not (yet?) supported by FastISel.  This isn’t an issue for us, because fast isel never worked for our extensions to base MIPS.  We’ve temporarily simply disabled fast isel entirely, but it would be nice if we could only include our .td file for the TableGen runs that are *not* generating the fast isel code.

Looking at the tablegen docs, I can’t see any mechanism that allows me to conditionally include a file.  Does this exist in any form?


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