[llvm-dev] Memory accesses and determining aliasing at the MI level

Hal Finkel via llvm-dev llvm-dev at lists.llvm.org
Fri May 19 19:52:14 PDT 2017


Hi, Martin,

If the MIs have MMOs attached (Machine Memory Operands), then you can 
use MI->mayAlias(AA, MI2, true) to check. This will use alias analysis 
if available. If you look at the implementation, you'll also see how to 
use AA based on the MMOs.

Also, saying "same base pointer" might get a bit tricky after stack 
coloring.

  -Hal

On 05/18/2017 09:41 AM, Martin J. O'Riordan via llvm-dev wrote:
> In order to implement a subtle memory access optimisation during post-RA
> scheduling, I want to be able to determine some properties about the memory
> access.
>
> If I have two registers referring to memory, how can I determine if they are
> derived from the same base-pointer?  Often LLVM will optimise to use
> intermediate registers holding partial displacements, for example, when a
> 'struct' object is on the stack, the address of the start of that object
> might be computed as:
>
>      R1 := SP + initialDisplacement;
>
> then the access to a member of that object may be accessed with a member
> offset from 'R1'.  This can get more complicated with larger examples where
> a series of intermediate registers with different displacements occur, yet
> they may all derive from a common ancestor base-pointer (the SP being the
> most common).
>
> What I would like to determine, is during post-RA scheduling, and given 2
> registers 'R1' and 'R2' referring to memory:
>
> 1.  Do 'R1' and 'R2' share a common base-pointer?
> 2.  For 'R1' and 'R2', what is the summary displacement from their
> respective base-pointers?
>
> Is this possible in post-RA at the MI level and if so how I can do this, or
> would I have to write an earlier pass to annotate the IR with the
> information I am looking for?
>
> Thanks,
>
>      MartinO
>
>
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-- 
Hal Finkel
Lead, Compiler Technology and Programming Languages
Leadership Computing Facility
Argonne National Laboratory



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