[llvm-dev] Bug in TableGen RegisterBankEmitter

Quentin Colombet via llvm-dev llvm-dev at lists.llvm.org
Wed May 10 08:58:07 PDT 2017


Hi Tom,

> On May 10, 2017, at 7:15 AM, Tom Stellard via llvm-dev <llvm-dev at lists.llvm.org> wrote:
> 
> Hi,
> 
> I've run into an issue with the RegisterBankEmitter on the AMDGPU backend.
> AMDGPU has a register class: VS_32, which is non-allocatable and contains
> registers from both defined register banks (SGPRRegBank and VGPRRegBank).
> 
> The RegisterBankEmitter is adding this class to the CoverageData array
> for both register classes, because it contains sub-registers of one
> of the classes explicitly added to the RegisterBank, for example:
> 
> Added VS_32(explicit (VS_32) VReg_64 class-with-subregs: VReg_64)
> 
> This is a problem, because both RegisterBanks think they cover
> VS_32, even though neither of them actually do.

I agree this is a bug in the emitter. It should only add the subclasses of VS_32 that projects to V (resp. S) for the given subregs.

I let Daniel comment further.

Cheers,
-Quentin

> 
> What exactly is the best way to fix this?  It seems like we need some
> additional checks in the RegisterBankEmitter to fix this, but it's not
> clear to me what we should be checking for.
> 
> Thanks,
> Tom
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