[llvm-dev] problem with non-allocatable register classes

[Davis, Alan via llvm-dev]

OK, to follow up to my own post, I made a fix in firstCommonClass (copied below for reference). I'm not convinced about the fix, but I am convinced that the code as written is at least partially wrong. The function is looping through the subclass bitvectors of two register classes, looking for the first common subclass. The main loop is looping through the bitvectors word by word. It's possible that in any given word there is more than one common bit. The code checks the first (rightmost bit). If that class is disqualified by the type check, it loops to the next word rather than checking other bits in the current word.

So my fix has two parts. First: add isAllocatable() to the qualification check. Second: add an inner loop so that if the qualification check fails, we'll iterate on the other common bits in the current word.

I'm looking for a little confirmation that this seems sensible, since I'm new to LLVM.

-Alan

static inline
const TargetRegisterClass *firstCommonClass(const uint32_t *A,
                                            const uint32_t *B,
                                            const TargetRegisterInfo *TRI,
                                            const MVT::SimpleValueType SVT =
                                            MVT::SimpleValueType::Any) {
  const MVT VT(SVT);
  for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32)
    if (unsigned Common = *A++ & *B++) {
      const TargetRegisterClass *RC =
          TRI->getRegClass(I + countTrailingZeros(Common));
      if (SVT == MVT::SimpleValueType::Any || RC->hasType(VT))
        return RC;
    }
  return nullptr;
}

From: Davis, Alan
Sent: Thursday, May 04, 2017 9:35 PM
To: llvm-dev at lists.llvm.org
Subject: problem with non-allocatable register classes

I am using some non-allocatable RegisterClasses to define lists of registers that are used for various non-allocation-related processing in the back end. For example, we have a post-allocation functional unit selection pass that is guided by the register assignment, which does things like 'myRegClass.contains(Reg)' to see if a register is in the set of registers accessible by a given unit.

These sets contain lists of both allocatable and non-allocatable registers (for example, GPRs plus PC and SP). So I defined them as non-allocatable, and defined separate classes for use in the allocator.

The problem is that tablegen does all kinds of clever analysis of the register classes, determining subsets and supersets and such, which are used to answer methods like getCommonSubClass(). In some cases it synthesizes new classes, which may or may not be allocatable depending on how the non-allocatable classes get mixed in. If a function like getCommonSubClass() returns a non-allocatable class, bad things happen (e.g. assertion failures from setRegClass()).

It seems to me that functions like getCommonSubClass() should never return non-allocatable classes. But there seems to be no provision in tablegen to keep that from happening. It seems likely that no one has encountered this because for most targets non-allocatable classes contain registers that don't overlap much with the allocatable classes.

Does anyone have any guidance as far as fixing or working around this?

-Alan
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