[llvm-dev] Code selection problem in LLVM backend

[Roel Jordans via llvm-dev]

Hi Winter,


I'm not sure what went wrong then, maybe you missed adding these flags 
somewhere.


I suggest taking a small test-case which has this behavior and pushing 
it through llc with the -debug flag.  That should show the instruction 
graph after many of the selection and scheduling stages.  Check if the 
input graph of the scheduling stage indeed now has the new flags 
register marked as a dependency between the cmp and beq operations.  
That should also show the add and store operations and hopefully 
demonstrate that the add operations are now also marked as clobering the 
flags register.


Cheers,

  Roel


On 23-03-17 13:23, Liu winter wrote:
>
> Hi Roel,
>
>
> Thanks a lot for your advice, I have added "Defs" and "implicit" 
> syntax of status register in the related instructions. However, it 
> seems that it couldn't take effect. I would describe more details.
>
>
> In my case, the "add" after "cmp" is used to calculate address due to 
> the limitation of addressing mode, for example,
>
>
> ...
>
> cmp r8, r9
>
> add r14, sp, 19
>
> store [r14], r7
>
> add r14, sp, 18
>
> store [r14], r6
>
> beq LBB02
>
> ...
>
>
> I have another try on AVR. The corresponding code is
>
>
> ...
>
> cp   r24,   r18
>
> cpc r25,   r19
>
> std Y+9,   r18
>
> std Y+10, r31
>
> brne LBB0_1
>
> rjmp LBB0_2
>
> ....
>
>
> I haved added "Defs = [SREG]" and "(implicit SREG)" in the definition 
> of "std" instruction SDNode, i.e. "STDPtrQRr", but nothing happened. I 
> wonder
>
>
> 1. if I forget some important steps.
>
> 2. or llvm couldn't deal with the case related to "store".
>
>
> Yours,
>
> winter
>
>
>
> ------------------------------------------------------------------------
> *From:* Roel Jordans <r.jordans at tue.nl>
> *Sent:* March 22, 2017 1:16
> *To:* Liu winter
> *Subject:* Re: [llvm-dev] Code selection problem in LLVM backend
>
> Hi,
>
>
> You can define the status register in your register infor and then 
> mark all operations that define/use the status register.  For an 
> example you can look at the AVR backend which uses this technique.
>
>
> Cheers,
>
>  Roel
>
>
> On 22-03-17 04:03, Liu winter via llvm-dev wrote:
>>
>> Hi,
>>
>>
>> I'm currently writing a backend for a specific platform. On the 
>> target platform, "add/sub" always write a flag result. I used SDNode 
>> pattern "add/sub" for these  two instructions, however this leading 
>> to a wrongly code as follows,
>>
>>
>> cmp
>>
>> ...
>>
>> add ...
>>
>> ...
>>
>> beq
>>
>>
>> "add" changes the flag. Desired code is:
>>
>>
>> add...
>>
>> cmp
>>
>> ...         ;No add/sub
>>
>> beq
>>
>>
>> Then I tried to use SDNode pattern "addc/subc" instead, but it 
>> doesn't matter and cause some other errors. What should I do to 
>> generate code that no "add/sub" between "cmp" and "branch"?
>>
>

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