[llvm-dev] Wide load/store optimization question

Matthias Braun via llvm-dev llvm-dev at lists.llvm.org
Fri Jun 16 17:05:46 PDT 2017

> On Jun 16, 2017, at 2:43 PM, 陳韋任 via llvm-dev <llvm-dev at lists.llvm.org> wrote:
> 2017-06-17 4:36 GMT+08:00 upcfrost <upcfrost at gmail.com <mailto:upcfrost at gmail.com>>:
> Hi,
> Same here, my backend only has 64bit load/store. But i still use 64bit virt regs and expand/declare missing instructions by myself. 
> I'll try looking into sparc backend, thanks. Also, only after writing this post I found a bunch of built-in transforms. Still trying to understand how to use those.
> By the way, constraint-wise (alignment), is there any difference between virt regclass and regtuple?

That question makes no sense.
- Every virtual register has a register class assigned.
- You can construct special register classes that represent register tuples so that when the allocator chooses an entry from that register class it really has choosen a tuple of machine registers (even though it looks like a single register with funny aliasing as far as llvm codegen is concerned).

- Matthias
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