[llvm-dev] Backend implementation for an architecture with only majority operation instruction

Sreejita saha via llvm-dev llvm-dev at lists.llvm.org
Mon Jun 5 14:12:16 PDT 2017

Hey Can you refer me to some documentation on manually creating a backend
without codegen?

On Mon, Jun 5, 2017 at 3:08 PM, Matthias Braun <mbraun at apple.com> wrote:

> On Jun 1, 2017, at 8:13 PM, Sreejita saha via llvm-dev <
> llvm-dev at lists.llvm.org> wrote:
> Hello everyone,
> I was trying to create an LLVM backend for a processor with a very simple
> architecture and that does all instructions like load, store, arithmetic
> and logical instructions using a bunch of majority functions. The processor
> has only one instruction(majority function) in its ISA and breaks down all
> other instructions into a number of majority instructions depending on what
> instruction it is. All the instructions have different combinations of
> majority operations. Is there any way to implement this without creating a
> new Selection DAG node for the majority operation?
> I was thinking of creation of a new Selection DAG node and mapping all the
> other instructions like loads, stores as pseudo instructions and breaking
> them up. Can someone please help me with this?
> If your architecture is alien enough (and so far this sounds pretty alien
> to me) it may make sense to just create a custom backend that goes from the
> IR representation to whatever machine format/assembly you are using.
> While CodeGen gives you a lot of infrastructure that fits "normal" CPUs
> well (ABI lowering, instruction selection, register allocation, scheduling,
> object file formats, debug info). On the other hand if your target is a
> hypothetical CPU (just making guesses from what little you wrote) you may
> not need all that:
> - Register allocation usually only makes sense if you have a bounded
> number of registers or special constraints.
> - Scheduling usually only makes sense if you have a machine model with
> different latencies or want to optimize register pressure to minimize spill
> reloads (for bounded number of regs).
> - If your object file format isn't ELF/macho/coff then you won't gain much
> from the MC infrastructure and debug generation infrastructure.
> If you don't need most of these things then you are probably better off
> manually implementing a TargetMachine without using CodeGen (instead of
> implementing an LLVMTargetMachine with all the CodeGen utilities).
> - Matthias
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