[llvm-dev] Backend implementation for an architecture with only majority operation instruction

[Sreejita saha via llvm-dev]

Hey Sean,
So the processor does in-memory computing, it reads instructions and
operands from the memory array, performs the majority operations within the
memory array itself.
It does instructions using resistive majority which is AB'+B'C+AC
Like it does AND operation as
1: 0, 1, @C; //C=0
2: 0, 1, @Binv; //Binv=0
3: 1, @B, @Binv; //Binv=B
4: @A, @Binv, @C; //C=A.B
 where each operation is a resistive majority and operations are directly
performed on the storage of C.  It reads @A in a register , @B , reads A
and B and directly writes into the memory @C. There are shift operators as
well that are also performed in a similar way, loads, stores are also
performed like this. So I am trying to define this resistive majority
instruction in my ISA.

Thanks!
-Sreejita


On Sun, Jun 4, 2017 at 8:22 PM, Sean Silva <chisophugis at gmail.com> wrote:

> I'm having a hard time grasping what this ISA actually looks like.
>
> When you say that it has a single instruction that is a majority function,
> I assume something like this:
>
> MAJ rDst <- rSrc0, rSrc1, rSrc2
> Semantics:
> for (int i = 0; i < REGISTER_WIDTH; i++) {
>   rDst[i] = maj(rSrc0[i], rSrc1[i], rSrc2[i]);
> }
> Where maj(a, b, c) = (a & b) | (a & c) | (b & c)
>
> But that doesn't make sense given your question.
>
> MAJ is a bitwise operation, so how do you implement arithmetic
> instructions with it? You would need at least one other instruction (such
> as a bit shift) to establish dependency chains between bits.
>
> Also, how do you decompose load/store into majority functions? It's not
> even clear to me what that would actually mean. You need to access the
> memory/IO bus somehow, and if your only instruction only reads/writes to
> registers, the only way to do that would be to have special registers that
> interface to the IO bus?
>
> -- Sean Silva
>
> On Thu, Jun 1, 2017 at 8:13 PM, Sreejita saha via llvm-dev <
> llvm-dev at lists.llvm.org> wrote:
>
>> Hello everyone,
>>
>>
>>
>> I was trying to create an LLVM backend for a processor with a very simple
>> architecture and that does all instructions like load, store, arithmetic
>> and logical instructions using a bunch of majority functions. The processor
>> has only one instruction(majority function) in its ISA and breaks down all
>> other instructions into a number of majority instructions depending on what
>> instruction it is. All the instructions have different combinations of
>> majority operations. Is there any way to implement this without creating a
>> new Selection DAG node for the majority operation?
>>
>> I was thinking of creation of a new Selection DAG node and mapping all
>> the other instructions like loads, stores as pseudo instructions and
>> breaking them up. Can someone please help me with this?
>>
>>
>>
>> Thanks!
>>
>> Sreejita
>>
>>
>>
>>
>>
>> Sent from Mail <https://go.microsoft.com/fwlink/?LinkId=550986> for
>> Windows 10
>>
>>
>>
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>>
>>
>
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