[llvm-dev] Deprecating the experimental microMIPS64R6 backend
Alex Elsayed via llvm-dev
llvm-dev at lists.llvm.org
Thu Jul 13 23:05:49 PDT 2017
On Thu, 13 Jul 2017 11:02:57 +0000, Simon Dardis via llvm-dev wrote:
>> -----Original Message-----
>> From: Dr D. Chisnall [mailto:dc552 at hermes.cam.ac.uk] On Behalf Of David
>> Chisnall Sent: 13 July 2017 11:22 To: Simon Dardis Cc:
>> llvm-dev at lists.llvm.org Subject: Re: [llvm-dev] Deprecating the
>> experimental microMIPS64R6 backend
>> On 13 Jul 2017, at 11:14, Simon Dardis via llvm-dev
>> <llvm-dev at lists.llvm.org>
>> > Hi all,
>> > I plan to deprecate the experimental microMIPS64R6 backend for the
>> > 5.0 release and remove it after the release.
>> > Currently there are no CPUs that use that particular sub-ISA which
>> > makes it difficult to justify the maintenance and parallel
>> > development
>> > If there was a CPU design produced that did use microMIPS64R6, the
>> > backend could be restored from the archive.
>> > Any comments or objections?
>> Are there any microMIPS or MIPS16 CPUs in the wild? There is a lot of
>> complexity in the MIPS back end to handle these, but I’ve never seen
>> one (and support for the far more common MIPS IV CPUs has suffered as a
>> result of the back end focusing on these variants).
> The Microchip PIC32 family support microMIPS, the m62xxx cpus support
> microMIPS32R6 and the interAptiv series of chips support MIPS16.
> All are currently available.
> If you're aware of any bugs or existing ones for the MIPS backend that
> need addressing, can you bring them to my attention?
For MIPS16, more than merely "available" - my router (a pretty common
model, especially for OpenWRT) supports it.
troot at OpenWrt:~# cat /proc/cpuinfo
system type : Qualcomm Atheros QCA9558 ver 1 rev 0
machine : TP-LINK Archer C7
processor : 0
cpu model : MIPS 74Kc V5.0
BogoMIPS : 358.80
wait instruction : yes
microsecond timers : yes
tlb_entries : 32
extra interrupt vector : yes
hardware watchpoint : yes, count: 4, address/irw mask: [0x0ffc,
0x0ffc, 0x0ffb, 0x0ffb]
isa : mips1 mips2 mips32r1 mips32r2
ASEs implemented : mips16 dsp dsp2
shadow register sets : 1
kscratch registers : 0
package : 0
core : 0
VCED exceptions : not available
VCEI exceptions : not available
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