[llvm-dev] Unhandled reg/opcode register encoding VR2048 Error in backend

[hameeza ahmed via llvm-dev]

Hello,
I m working towards  backend.
Here i need to define vector load and stores for 64 i32 elements. so in
x86instrinfo.td i wrote;

 def VMOV_256B_RM : I<0x6F, MRMSrcMem, (outs VR2048:$dst), (ins
i32mem:$src),
                    "vmov_256B_rm\t{$src, $dst|$dst, $src}",
                    [(set VR2048:$dst, (v64i32 (scalar_to_vector (loadi32
addr:$src))))],
                    IIC_MOV_MEM>, EVEX;

def VMOV_256B_MR : I<0x7F, MRMDestMem, (outs), (ins i32mem:$dst,
VR2048:$src),
                    "vmov_256B_mr\t{$src, $dst|$dst, $src}",
                    [(store (i32 (bitconvert VR2048:$src)), addr:$dst)],
IIC_MOV_MEM>, EVEX;

here i have already define VR2048 in x86registerinfo.td as;

def R256B_0: X86Reg<"R256B_0", 0>;
def R256B_1: X86Reg<"R256B_1", 1>;
def VR2048 : RegisterClass<"X86", [v64i32],
                          2048, (add R256B_0, R256B_1)


Now when build llvm source i am getting following error:

Unhandled reg/opcode register encoding VR2048
Unhandled reg/opcode register encoding

Where i am wrong, please correct me;

I need  help.

Thank you
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20170707/50ed7e9e/attachment.html>