[llvm-dev] vector wideing for vector SETCC / VSELECT

Friedman, Eli via llvm-dev llvm-dev at lists.llvm.org
Thu Jan 26 14:50:55 PST 2017

On 1/26/2017 7:54 AM, Jonas Paulsson wrote:
> Hi Eli (and all),
> There is on SystemZ a similar problem to that of the sext/zext 
> operations on partial vectors, that we just handled with vector 
> widening. The same problem of many useless instructions happen with 
> vector compare / select instructions if the vector registers only 
> contain a few elements.
> This seems a bit trickier. I tried to return TypeWidenVector in 
> getPreferredVectorAction() for vectors of i1s, but this didn't seem to 
> work at all - this actually ended up giving TypeSplitVector for the 
> v2i1 vector, which resulted in an infinite loop even.
> So I wanted to say "if doing a vector compare & select, just work with 
> the full registers" (vector widening).
> I don't have any idea what to do other than trying to do something 
> custom or so. Does anyone have any advice to give on this?

Have you looked at DAGTypeLegalizer::PromoteTargetBoolean and 
DAGTypeLegalizer::WidenTargetBoolean ?  I don't remember all the details 
off the top of my head, but we can't use the normal vector widening 
utilities because there isn't one right answer.


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