[llvm-dev] Changes to TableGen in v4.0?
Martin J. O'Riordan via llvm-dev
llvm-dev at lists.llvm.org
Mon Jan 23 03:41:17 PST 2017
I am trying to upgrade to the LLVM v4.0 branch, but I am seeing failures in
my TableGen descriptions for conversion from FP32 to FP16 (scalar and
The patterns I have are along the lines of:
[(set (f16 RF16:$dst), (fround (f32 RF32:$src)))]
[(set (v2f16 VF16:$dst), (fround (v2f32 VF32:$src)))]
and these now produce the errors:
error: In CONV_f32_f16: Type inference contradiction found, merging 'f32'
error: In CONV_v2f32_v2f16: Type inference contradiction found, merging
'v2f32' into 'v2f16'
For the scalar version, the conflict is between two rules that have
different mutually exclusive predicates (for alternative chip versions).
But in the case of the vector, the conflict is for a vector of a different
size, in the case:
[(set (v4f16 VF16:$dst), (fround (v4f32 VF32:$src)))]
and 'CONV_v4f32_v4f16'. What adjustments do I need to make to the TD
descriptions to make these work again? I know that FP16 is not hugely
common on the mainstream platforms, but it is vital to ours.
I did notice that 'fextend' was replaced by 'fpextend', is there some new
ISD node type I should use for 'fround'?
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