[llvm-dev] Got stuck with PC-rel branching

Peter Bel via llvm-dev llvm-dev at lists.llvm.org
Thu Jan 19 09:11:28 PST 2017

Hi all,

I'm trying to make an LLVM backend for the Adapteva's Epiphany E16 CPU
(used in Parallella board), using CPU0 and some other backends as examples,
and I've got stuck with branching.

When I'm printing out asm, all branch labels are printed as they should be.
But when I'm trying to generate obj file, I'm getting zeros instead of
PC-related offset in all branch instructions.

In short, what I'm doing:

- Pattern (br bb:$addr) is selected using EpiphanyInstrInfo.td as
BNONE32(ins jmptarget:$addr), Branch32 class

- Branch32 class is defined in EpiphanyInstrFormats.td with bits<24> addr,
which should go into bits{31-8} of the MC instruction. Those bits remain
zeros after relaxation for some reason.

- jmptarget operand has type OPERAND_PCREL, and uses EncoderMethod
"getJumpTargetOpValue" defined in EpiphanyMCCodeEmitter. If this method
gets MCExpr, it creates fixup, and I can see this fixup in debug.

- Fixup is called fixup_Epiphany_PCREL24, and is defined in
EpiphanyFixupKinds and EpiphanyAsmBackend, with FKF_IsPCRel flag.

Can someone please tell me if I am missing something?

The source itself can be found at

Debug output on pastebin: http://pastebin.com/8uKRv0qK



P.S. sorry for messy code, I knew nothing about LLVM backends when I
started, so the code have copy-paste in more than one place.
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