[llvm-dev] Tweaking the Register Allocator's spill placement

[Quentin Colombet via llvm-dev]

Hi Nick,

> On Jan 9, 2017, at 2:55 PM, Johnson, Nicholas Paul via llvm-dev <llvm-dev at lists.llvm.org> wrote:
> 
> Hello,
> 
> My target features some very-high-latency instructions that access an on-chip network (we'll call them FXLV).  In one important kernel (snippet below), register allocation needs to spill values resulting from FXLV.  The spiller is unaware of FXLV's latency, and thus naively inserts those spills immediately after the FXLV, incurring huge and unnecessary data stalls.  
> 
>    FXLV r10, 0(r3.0)
>    SV r10, 0(r63.1) # spill to stack slot
>    FXLV r10, 16(r3.0)
>    SV r10, 16(r63.1) # spill to stack slot
>    FXLV r10, 32(r3.0)
>    SV r10, 32(r63.1) # spill to stack slot
>    FXLV r10, 48(r3.0)
>    SV r10, 48(r63.1) # spill to stack slot
>    ...
> Note also how the register allocator unfortunately re-uses register r10.  This prevents Post-RA scheduling from helping.
> 
> 
> 
> A better sequence of spills would hide the latency thusly:
>    FXLV r10, 0(r3.0)
>    FXLV r11, 16(r3.0)
>    FXLV r12, 32(r3.0)
>    FXLV r13, 48(r3.0)
>    ...
>    SV r10, 0(r63.1) # spill to stack slot
>    SV r11, 16(r63.1) # spill to stack slot
>    SV r12, 32(r63.1) # spill to stack slot
>    SV r13, 48(r63.1) # spill to stack slot
>    ...  
> 
> Any suggestions of how I could achieve this better spill sequence?  Do I need to write a target-specific implementation of InlineSpiller?

Have you tried to run the post RA scheduler?

The problem with spilling is that you want to keep the live-range in register as short as possible because otherwise you may need to spill more.

Cheers,
-Quentin
> 
> Thanks,
> Nick Johnson
> D. E. Shaw Research
> 
> 
> 
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