[llvm-dev] When AVR backend generates mulsu instruction ?
vivek pandya via llvm-dev
llvm-dev at lists.llvm.org
Sun Feb 26 03:41:59 PST 2017
I am looking for an example for how to lower LLVM IR to mulsu kind of
instruction. I found that AVR back end have such instruction but
AVRInstrInfo.td does not define any DAG pattern for which this
instruction gets emitted.
def MULSURdRr : FMUL2RdRr<1,
(ins GPR8:$lhs, GPR8:$rhs),
Also simple grep around related words does not show any other information.
Can some one explain me how this kind of instruction should be lowered ?
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